flush_icache();
}
-void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
+reg_t mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
{
reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
reg_t expected_tag = addr & ~(PGSIZE-1);
tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
- tlb_data[idx] = (char*)mem + pgbase;
+ tlb_data[idx] = pgbase;
}
- return (char*)mem + paddr;
+ return paddr;
}
pte_t mmu_t::walk(reg_t addr)