new supervisor mode

[riscv-isa-sim.git] / riscv / mmu.cc

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 55273f328d7f5222ae9c417b24f603997baccf93..c8eec16a6f4156ce0c253f3b92d37e4a0f18354d 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -63,7 +63,7 @@ pte_t mmu_t::walk(reg_t addr)
 
   // the address must be a canonical sign-extended VA_BITS-bit number
   int shift = 8*sizeof(reg_t) - VA_BITS;
-  if (((sreg_t)addr << shift >> shift) != addr)
+  if (((sreg_t)addr << shift >> shift) != (sreg_t)addr)
     ;
   else if(!vm_enabled)
   {