#include "sim.h"
#include "processor.h"
+#define LEVELS(xlen) ((xlen) == 32 ? 2 : 3)
+#define PPN_SHIFT(xlen) ((xlen) == 32 ? 10 : 26)
+#define PTIDXBITS(xlen) ((xlen) == 32 ? 10 : 9)
+#define VPN_BITS(xlen) (PTIDXBITS(xlen) * LEVELS(xlen))
+#define VA_BITS(xlen) (VPN_BITS(xlen) + PGSHIFT)
+
mmu_t::mmu_t(char* _mem, size_t _memsz)
: mem(_mem), memsz(_memsz), proc(NULL)
{
void mmu_t::flush_icache()
{
- memset(icache_tag, -1, sizeof(icache_tag));
+ for (size_t i = 0; i < ICACHE_ENTRIES; i++)
+ icache[i].tag = -1;
}
void mmu_t::flush_tlb()
flush_icache();
}
-reg_t mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
+void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
{
reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
- reg_t expected_tag = addr & ~(PGSIZE-1);
-
- reg_t pte = walk(addr);
-
- reg_t pte_perm = pte & PTE_PERM;
- if (proc == NULL || (proc->state.sr & SR_S))
- pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
- pte_perm |= pte & PTE_V;
-
- reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_V;
- if(unlikely((pte_perm & perm) != perm))
- {
- if (fetch)
- throw trap_instruction_access_fault();
-
- if (store)
- throw trap_store_access_fault(addr);
- throw trap_load_access_fault(addr);
+ reg_t expected_tag = addr >> PGSHIFT;
+
+ reg_t mstatus = proc ? proc->state.mstatus : 0;
+
+ bool vm_disabled = get_field(mstatus, MSTATUS_VM) == VM_MBARE;
+ bool mode_m = get_field(mstatus, MSTATUS_PRV) == PRV_M;
+ bool mode_s = get_field(mstatus, MSTATUS_PRV) == PRV_S;
+ bool mprv_m = get_field(mstatus, MSTATUS_MPRV) == PRV_M;
+ bool mprv_s = get_field(mstatus, MSTATUS_MPRV) == PRV_S;
+
+ reg_t pgbase;
+ if (vm_disabled || (mode_m && (mprv_m || fetch))) {
+ pgbase = addr & -PGSIZE;
+ // virtual memory is disabled. merely check legality of physical address.
+ if (addr >= memsz)
+ pgbase = -1;
+ } else {
+ pgbase = walk(addr, mode_s || (mode_m && mprv_s), store, fetch);
}
reg_t pgoff = addr & (PGSIZE-1);
- reg_t pgbase = pte >> PGSHIFT << PGSHIFT;
reg_t paddr = pgbase + pgoff;
+ if (pgbase == reg_t(-1)) {
+ if (fetch) throw trap_instruction_access_fault(addr);
+ else if (store) throw trap_store_access_fault(addr);
+ else throw trap_load_access_fault(addr);
+ }
+
if (unlikely(tracer.interested_in_range(pgbase, pgbase + PGSIZE, store, fetch)))
tracer.trace(paddr, bytes, store, fetch);
else
{
- tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
- tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
- tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
- tlb_data[idx] = pgbase;
+ if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
+ if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
+ if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
+
+ if (fetch) tlb_insn_tag[idx] = expected_tag;
+ else if (store) tlb_store_tag[idx] = expected_tag;
+ else tlb_load_tag[idx] = expected_tag;
+
+ tlb_data[idx] = mem + pgbase - (addr & ~(PGSIZE-1));
}
- return paddr;
+ return mem + paddr;
}
-pte_t mmu_t::walk(reg_t addr)
+reg_t mmu_t::walk(reg_t addr, bool supervisor, bool store, bool fetch)
{
- pte_t pte = 0;
-
- // the address must be a canonical sign-extended VA_BITS-bit number
- int shift = 8*sizeof(reg_t) - VA_BITS;
- if (((sreg_t)addr << shift >> shift) != (sreg_t)addr)
- ;
- else if (proc == NULL || !(proc->state.sr & SR_VM))
- {
- if(addr < memsz)
- pte = PTE_V | PTE_PERM | ((addr >> PGSHIFT) << PGSHIFT);
- }
- else
- {
- reg_t base = proc->get_state()->ptbr;
- reg_t ptd;
-
- int ptshift = (LEVELS-1)*PTIDXBITS;
- for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
- {
- reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
-
- reg_t pte_addr = base + idx*sizeof(pte_t);
- if(pte_addr >= memsz)
- break;
-
- ptd = *(pte_t*)(mem+pte_addr);
-
- if (!(ptd & PTE_V)) // invalid mapping
- break;
- else if (ptd & PTE_T) // next level of page table
- base = (ptd >> PGSHIFT) << PGSHIFT;
- else // the actual PTE
- {
- // if this PTE is from a larger PT, fake a leaf
- // PTE so the TLB will work right
- reg_t vpn = addr >> PGSHIFT;
- ptd |= (vpn & ((1<<(ptshift))-1)) << PGSHIFT;
-
- // fault if physical addr is out of range
- if (((ptd >> PGSHIFT) << PGSHIFT) < memsz)
- pte = ptd;
- break;
- }
+ reg_t msb_mask = -(reg_t(1) << (VA_BITS(proc->xlen) - 1));
+ if ((addr & msb_mask) != 0 && (addr & msb_mask) != msb_mask)
+ return -1; // address isn't properly sign-extended
+
+ reg_t base = proc->get_state()->sptbr;
+
+ int xlen = proc->max_xlen;
+ int ptshift = (LEVELS(xlen) - 1) * PTIDXBITS(xlen);
+ for (reg_t i = 0; i < LEVELS(xlen); i++, ptshift -= PTIDXBITS(xlen)) {
+ reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS(xlen))-1);
+
+ // check that physical address of PTE is legal
+ reg_t pte_addr = base + idx*sizeof(reg_t);
+ if (pte_addr >= memsz)
+ return -1;
+
+ reg_t* ppte = (reg_t*)(mem+pte_addr);
+ reg_t ppn = *ppte >> PPN_SHIFT(xlen);
+
+ if ((*ppte & PTE_TYPE) == PTE_TYPE_TABLE) { // next level of page table
+ base = ppn << PGSHIFT;
+ } else {
+ // we've found the PTE. check the permissions.
+ if (!PTE_CHECK_PERM(*ppte, supervisor, store, fetch))
+ return -1;
+ // set referenced and possibly dirty bits.
+ *ppte |= PTE_R;
+ if (store)
+ *ppte |= PTE_D;
+ // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
+ reg_t vpn = addr >> PGSHIFT;
+ reg_t addr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
+
+ // check that physical address is legal
+ if (addr >= memsz)
+ return -1;
+
+ return addr;
}
}
- return pte;
+ return -1;
}
void mmu_t::register_memtracer(memtracer_t* t)
projects / riscv-isa-sim.git / blobdiff