Merge pull request #156 from p12nGH/noncontiguous_harts

[riscv-isa-sim.git] / riscv / mmu.h

diff --git a/riscv/mmu.h b/riscv/mmu.h
index f70a969be48eba4a148d25c8b9684d789bbb2cb3..7d6ea88be5cfbc4ac766ffadd25b621c10e4b6c9 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -151,6 +151,25 @@ public:
       } \
     }
 
+  void store_float128(reg_t addr, float128_t val)
+  {
+#ifndef RISCV_ENABLE_MISALIGNED
+    if (unlikely(addr & (sizeof(float128_t)-1)))
+      throw trap_store_address_misaligned(addr);
+#endif
+    store_uint64(addr, val.v[0]);
+    store_uint64(addr + 8, val.v[1]);
+  }
+
+  float128_t load_float128(reg_t addr)
+  {
+#ifndef RISCV_ENABLE_MISALIGNED
+    if (unlikely(addr & (sizeof(float128_t)-1)))
+      throw trap_load_address_misaligned(addr);
+#endif
+    return (float128_t){load_uint64(addr), load_uint64(addr + 8)};
+  }
+
   // store value to memory at aligned address
   store_func(uint8)
   store_func(uint16)