#include "trap.h"
#include "common.h"
#include "config.h"
+#include "sim.h"
#include "processor.h"
#include "memtracer.h"
+#include <stdlib.h>
#include <vector>
// virtual memory configuration
-typedef reg_t pte_t;
-const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
-const reg_t PTIDXBITS = 10;
-const reg_t PGSHIFT = PTIDXBITS + (sizeof(pte_t) == 8 ? 3 : 2);
+#define PGSHIFT 12
const reg_t PGSIZE = 1 << PGSHIFT;
-const reg_t VPN_BITS = PTIDXBITS * LEVELS;
-const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT;
-const reg_t VA_BITS = VPN_BITS + PGSHIFT;
struct insn_fetch_t
{
class mmu_t
{
public:
- mmu_t(char* _mem, size_t _memsz);
+ mmu_t(sim_t* sim, processor_t* proc);
~mmu_t();
// template for functions that load an aligned value from memory
#define load_func(type) \
type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
- void* paddr = translate(addr, sizeof(type##_t), false, false); \
- return *(type##_t*)paddr; \
+ if (addr & (sizeof(type##_t)-1)) \
+ throw trap_load_address_misaligned(addr); \
+ reg_t vpn = addr >> PGSHIFT; \
+ if (likely(tlb_load_tag[vpn % TLB_ENTRIES] == vpn)) \
+ return *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr); \
+ type##_t res; \
+ load_slow_path(addr, sizeof(type##_t), (uint8_t*)&res); \
+ return res; \
}
// load value from memory at aligned address; zero extend to register width
// template for functions that store an aligned value to memory
#define store_func(type) \
void store_##type(reg_t addr, type##_t val) { \
- void* paddr = translate(addr, sizeof(type##_t), true, false); \
- *(type##_t*)paddr = val; \
+ if (addr & (sizeof(type##_t)-1)) \
+ throw trap_store_address_misaligned(addr); \
+ reg_t vpn = addr >> PGSHIFT; \
+ if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
+ *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr) = val; \
+ else \
+ store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&val); \
}
// store value to memory at aligned address
inline size_t icache_index(reg_t addr)
{
- // for instruction sizes != 4, this hash still works but is suboptimal
- return (addr / 4) % ICACHE_ENTRIES;
+ return (addr / PC_ALIGN) % ICACHE_ENTRIES;
}
- // load instruction from memory at aligned address.
- icache_entry_t* access_icache(reg_t addr) __attribute__((always_inline))
+ inline icache_entry_t* refill_icache(reg_t addr, icache_entry_t* entry)
{
- reg_t idx = icache_index(addr);
- icache_entry_t* entry = &icache[idx];
- if (likely(entry->tag == addr))
- return entry;
+ const uint16_t* iaddr = translate_insn_addr(addr);
+ insn_bits_t insn = *iaddr;
+ int length = insn_length(insn);
- bool rvc = false; // set this dynamically once RVC is re-implemented
- char* iaddr = (char*)translate(addr, rvc ? 2 : 4, false, true);
- insn_bits_t insn = *(uint16_t*)iaddr;
-
- if (unlikely(insn_length(insn) == 2)) {
+ if (likely(length == 4)) {
+ insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 2) << 16;
+ } else if (length == 2) {
insn = (int16_t)insn;
- } else if (likely(insn_length(insn) == 4)) {
- if (likely((addr & (PGSIZE-1)) < PGSIZE-2))
- insn |= (insn_bits_t)*(int16_t*)(iaddr + 2) << 16;
- else
- insn |= (insn_bits_t)*(int16_t*)translate(addr + 2, 2, false, true) << 16;
- } else if (insn_length(insn) == 6) {
- insn |= (insn_bits_t)*(int16_t*)translate(addr + 4, 2, false, true) << 32;
- insn |= (insn_bits_t)*(uint16_t*)translate(addr + 2, 2, false, true) << 16;
+ } else if (length == 6) {
+ insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 4) << 32;
+ insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 2) << 16;
} else {
static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t");
- insn |= (insn_bits_t)*(int16_t*)translate(addr + 6, 2, false, true) << 48;
- insn |= (insn_bits_t)*(uint16_t*)translate(addr + 4, 2, false, true) << 32;
- insn |= (insn_bits_t)*(uint16_t*)translate(addr + 2, 2, false, true) << 16;
+ insn |= (insn_bits_t)*(const int16_t*)translate_insn_addr(addr + 6) << 48;
+ insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 4) << 32;
+ insn |= (insn_bits_t)*(const uint16_t*)translate_insn_addr(addr + 2) << 16;
}
insn_fetch_t fetch = {proc->decode_insn(insn), insn};
- icache[idx].tag = addr;
- icache[idx].data = fetch;
-
- reg_t paddr = iaddr - mem;
- if (!tracer.empty() && tracer.interested_in_range(paddr, paddr + 1, false, true))
- {
- icache[idx].tag = -1;
- tracer.trace(paddr, 1, false, true);
+ entry->tag = addr;
+ entry->data = fetch;
+
+ reg_t paddr = sim->mem_to_addr((char*)iaddr);
+ if (tracer.interested_in_range(paddr, paddr + 1, FETCH)) {
+ entry->tag = -1;
+ tracer.trace(paddr, length, FETCH);
}
- return &icache[idx];
+ return entry;
+ }
+
+ inline icache_entry_t* access_icache(reg_t addr)
+ {
+ icache_entry_t* entry = &icache[icache_index(addr)];
+ if (likely(entry->tag == addr))
+ return entry;
+ return refill_icache(addr, entry);
}
inline insn_fetch_t load_insn(reg_t addr)
return access_icache(addr)->data;
}
- void set_processor(processor_t* p) { proc = p; flush_tlb(); }
-
void flush_tlb();
void flush_icache();
void register_memtracer(memtracer_t*);
private:
- char* mem;
- size_t memsz;
+ sim_t* sim;
processor_t* proc;
memtracer_list_t tracer;
+ uint16_t fetch_temp;
// implement an instruction cache for simulator performance
icache_entry_t icache[ICACHE_ENTRIES];
reg_t tlb_store_tag[TLB_ENTRIES];
// finish translation on a TLB miss and upate the TLB
- void* refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
+ void refill_tlb(reg_t vaddr, reg_t paddr, access_type type);
// perform a page table walk for a given VA; set referenced/dirty bits
- pte_t walk(reg_t addr, bool store);
-
- // translate a virtual address to a physical address
- void* translate(reg_t addr, reg_t bytes, bool store, bool fetch)
- __attribute__((always_inline))
- {
- reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
- reg_t expected_tag = addr >> PGSHIFT;
- reg_t* tags = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
- reg_t tag = tags[idx];
- void* data = tlb_data[idx] + addr;
-
- if (unlikely(addr & (bytes-1)))
- store ? throw trap_store_address_misaligned(addr) :
- fetch ? throw trap_instruction_address_misaligned(addr) :
- throw trap_load_address_misaligned(addr);
-
- if (likely(tag == expected_tag))
- return data;
-
- return refill_tlb(addr, bytes, store, fetch);
+ reg_t walk(reg_t addr, access_type type, bool supervisor, bool pum);
+
+ // handle uncommon cases: TLB misses, page faults, MMIO
+ const uint16_t* fetch_slow_path(reg_t addr);
+ void load_slow_path(reg_t addr, reg_t len, uint8_t* bytes);
+ void store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes);
+ reg_t translate(reg_t addr, access_type type);
+
+ // ITLB lookup
+ const uint16_t* translate_insn_addr(reg_t addr) __attribute__((always_inline)) {
+ reg_t vpn = addr >> PGSHIFT;
+ if (likely(tlb_insn_tag[vpn % TLB_ENTRIES] == vpn))
+ return (uint16_t*)(tlb_data[vpn % TLB_ENTRIES] + addr);
+ return fetch_slow_path(addr);
}
friend class processor_t;
projects / riscv-isa-sim.git / blobdiff