On misaligned fetch, set EPC to target, not branch itself

[riscv-isa-sim.git] / riscv / mmu.h

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 08d41be012b52fda13b5b46e9437da91b90d775d..d24ed187bf30e1f868c8a059c133b771c39e9b46 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -167,7 +167,9 @@ private:
     void* data = tlb_data[idx] + addr;
 
     if (unlikely(addr & (bytes-1)))
-      store ? throw trap_store_address_misaligned(addr) : throw trap_load_address_misaligned(addr);
+      store ? throw trap_store_address_misaligned(addr) :
+      fetch ? throw trap_instruction_address_misaligned(addr) :
+      throw trap_load_address_misaligned(addr);
 
     if (likely(tag == expected_tag))
       return data;