Add debug module authentication.

[riscv-isa-sim.git] / riscv / mmu.h

diff --git a/riscv/mmu.h b/riscv/mmu.h
index e39cd94ad6116c2470e08bc6782c135fa8e69189..d275ab2baa2e412319c0a6ada72f41b932058e14 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -26,7 +26,7 @@ struct insn_fetch_t
 
 struct icache_entry_t {
   reg_t tag;
-  reg_t pad;
+  struct icache_entry_t* next;
   insn_fetch_t data;
 };
 
@@ -144,10 +144,10 @@ public:
         return lhs; \
       } catch (trap_load_page_fault& t) { \
         /* AMO faults should be reported as store faults */ \
-        throw trap_store_page_fault(t.get_badaddr()); \
+        throw trap_store_page_fault(t.get_tval()); \
       } catch (trap_load_access_fault& t) { \
         /* AMO faults should be reported as store faults */ \
-        throw trap_store_access_fault(t.get_badaddr()); \
+        throw trap_store_access_fault(t.get_tval()); \
       } \
     }
 
@@ -209,6 +209,7 @@ public:
 
     insn_fetch_t fetch = {proc->decode_insn(insn), insn};
     entry->tag = addr;
+    entry->next = &icache[icache_index(addr + length)];
     entry->data = fetch;
 
     reg_t paddr = tlb_entry.target_offset + addr;;