+// See LICENSE for license details.
+
+#ifndef _RISCV_MMU_H
+#define _RISCV_MMU_H
+
#include "decode.h"
#include "trap.h"
-#include "icsim.h"
+#include "common.h"
+#include "config.h"
+#include "processor.h"
+#include "memtracer.h"
+#include <vector>
+
+// virtual memory configuration
+typedef reg_t pte_t;
+const reg_t LEVELS = sizeof(pte_t) == 8 ? 3 : 2;
+const reg_t PGSHIFT = 12;
+const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2);
+const reg_t PGSIZE = 1 << PGSHIFT;
+const reg_t VPN_BITS = PTIDXBITS * LEVELS;
+const reg_t VA_BITS = VPN_BITS + PGSHIFT;
+
+struct insn_fetch_t
+{
+ insn_func_t func;
+ insn_t insn;
+};
-class processor_t;
+struct icache_entry_t {
+ reg_t tag;
+ reg_t pad;
+ insn_fetch_t data;
+};
+// this class implements a processor's port into the virtual memory system.
+// an MMU and instruction cache are maintained for simulator performance.
class mmu_t
{
public:
- mmu_t(char* _mem, size_t _memsz)
- : mem(_mem), memsz(_memsz), badvaddr(0),
- icsim(NULL), dcsim(NULL), itlbsim(NULL), dtlbsim(NULL)
- {
- }
-
- void set_icsim(icsim_t* _icsim) { icsim = _icsim; }
- void set_dcsim(icsim_t* _dcsim) { dcsim = _dcsim; }
- void set_itlbsim(icsim_t* _itlbsim) { itlbsim = _itlbsim; }
- void set_dtlbsim(icsim_t* _dtlbsim) { dtlbsim = _dtlbsim; }
-
- #ifdef RISCV_ENABLE_ICSIM
- # define dcsim_tick(dcsim, dtlbsim, addr, size, st) \
- do { if(dcsim) (dcsim)->tick(addr, size, st); \
- if(dtlbsim) (dtlbsim)->tick(addr, sizeof(reg_t), false); } while(0)
- #else
- # define dcsim_tick(dcsim, addr, size)
- #endif
+ mmu_t(char* _mem, size_t _memsz);
+ ~mmu_t();
+ // template for functions that load an aligned value from memory
#define load_func(type) \
- type##_t load_##type(reg_t addr) { \
- check_align_and_bounds(addr, sizeof(type##_t), false, false); \
- dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), false); \
- return *(type##_t*)(mem+addr); \
+ type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
+ void* paddr = translate(addr, sizeof(type##_t), false, false); \
+ return *(type##_t*)paddr; \
}
- #define store_func(type) \
- void store_##type(reg_t addr, type##_t val) { \
- check_align_and_bounds(addr, sizeof(type##_t), true, false); \
- dcsim_tick(dcsim, dtlbsim, addr, sizeof(type##_t), true); \
- *(type##_t*)(mem+addr) = val; \
- }
-
- insn_t load_insn(reg_t addr, bool rvc)
- {
- #ifdef RISCV_ENABLE_RVC
- check_align_and_bounds(addr, rvc ? 2 : 4, false, true);
- uint16_t lo = *(uint16_t*)(mem+addr);
- uint16_t hi = *(uint16_t*)(mem+addr+2);
-
- insn_t insn;
- insn.bits = lo | ((uint32_t)hi << 16);
-
- #ifdef RISCV_ENABLE_ICSIM
- if(icsim)
- icsim->tick(addr, insn_length(insn), false);
- if(itlbsim)
- itlbsim->tick(addr, sizeof(reg_t), false);
- #endif
-
- return insn;
- #else
- check_align_and_bounds(addr, 4, false, true);
- return *(insn_t*)(mem+addr);
- #endif
- }
-
+ // load value from memory at aligned address; zero extend to register width
load_func(uint8)
load_func(uint16)
load_func(uint32)
load_func(uint64)
+ // load value from memory at aligned address; sign extend to register width
load_func(int8)
load_func(int16)
load_func(int32)
load_func(int64)
+ // template for functions that store an aligned value to memory
+ #define store_func(type) \
+ void store_##type(reg_t addr, type##_t val) { \
+ void* paddr = translate(addr, sizeof(type##_t), true, false); \
+ *(type##_t*)paddr = val; \
+ }
+
+ // store value to memory at aligned address
store_func(uint8)
store_func(uint16)
store_func(uint32)
store_func(uint64)
- reg_t get_badvaddr() { return badvaddr; }
-
-private:
- char* mem;
- size_t memsz;
- reg_t badvaddr;
+ static const reg_t ICACHE_ENTRIES = 1024;
- icsim_t* icsim;
- icsim_t* dcsim;
- icsim_t* itlbsim;
- icsim_t* dtlbsim;
+ inline size_t icache_index(reg_t addr)
+ {
+ // for instruction sizes != 4, this hash still works but is suboptimal
+ return (addr / 4) % ICACHE_ENTRIES;
+ }
- void check_align(reg_t addr, int size, bool store, bool fetch)
+ // load instruction from memory at aligned address.
+ icache_entry_t* access_icache(reg_t addr) __attribute__((always_inline))
{
- if(addr & (size-1))
+ reg_t idx = icache_index(addr);
+ icache_entry_t* entry = &icache[idx];
+ if (likely(entry->tag == addr))
+ return entry;
+
+ char* iaddr = (char*)translate(addr, 1, false, true);
+ insn_bits_t insn = *(uint16_t*)iaddr;
+
+ if (likely(insn_length(insn) == 4)) {
+ if (likely(addr % PGSIZE < PGSIZE-2))
+ insn |= (insn_bits_t)*(int16_t*)(iaddr + 2) << 16;
+ else
+ insn |= (insn_bits_t)*(int16_t*)translate(addr + 2, 1, false, true) << 16;
+ } else if (insn_length(insn) == 2) {
+ insn = (int16_t)insn;
+ } else if (insn_length(insn) == 6) {
+ insn |= (insn_bits_t)*(int16_t*)translate(addr + 4, 1, false, true) << 32;
+ insn |= (insn_bits_t)*(uint16_t*)translate(addr + 2, 1, false, true) << 16;
+ } else {
+ static_assert(sizeof(insn_bits_t) == 8, "insn_bits_t must be uint64_t");
+ insn |= (insn_bits_t)*(int16_t*)translate(addr + 6, 1, false, true) << 48;
+ insn |= (insn_bits_t)*(uint16_t*)translate(addr + 4, 1, false, true) << 32;
+ insn |= (insn_bits_t)*(uint16_t*)translate(addr + 2, 1, false, true) << 16;
+ }
+
+ insn_fetch_t fetch = {proc->decode_insn(insn), insn};
+ icache[idx].tag = addr;
+ icache[idx].data = fetch;
+
+ reg_t paddr = iaddr - mem;
+ if (!tracer.empty() && tracer.interested_in_range(paddr, paddr + 1, false, true))
{
- badvaddr = addr;
- if(fetch)
- throw trap_instruction_address_misaligned;
- if(store)
- throw trap_store_address_misaligned;
- throw trap_load_address_misaligned;
+ icache[idx].tag = -1;
+ tracer.trace(paddr, 1, false, true);
}
+ return &icache[idx];
}
- void check_bounds(reg_t addr, int size, bool store, bool fetch)
+ inline insn_fetch_t load_insn(reg_t addr)
{
- if(addr >= memsz || addr + size > memsz)
- {
- badvaddr = addr;
- if(fetch)
- throw trap_instruction_access_fault;
- throw store ? trap_store_access_fault : trap_load_access_fault;
- }
+ return access_icache(addr)->data;
}
- void check_align_and_bounds(reg_t addr, int size, bool store, bool fetch)
+ void set_processor(processor_t* p) { proc = p; flush_tlb(); }
+
+ void flush_tlb();
+ void flush_icache();
+
+ void register_memtracer(memtracer_t*);
+
+private:
+ char* mem;
+ size_t memsz;
+ processor_t* proc;
+ memtracer_list_t tracer;
+
+ // implement an instruction cache for simulator performance
+ icache_entry_t icache[ICACHE_ENTRIES];
+
+ // implement a TLB for simulator performance
+ static const reg_t TLB_ENTRIES = 256;
+ char* tlb_data[TLB_ENTRIES];
+ reg_t tlb_insn_tag[TLB_ENTRIES];
+ reg_t tlb_load_tag[TLB_ENTRIES];
+ reg_t tlb_store_tag[TLB_ENTRIES];
+
+ // finish translation on a TLB miss and upate the TLB
+ void* refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch);
+
+ // perform a page table walk for a given VA; set referenced/dirty bits
+ pte_t walk(reg_t addr, bool supervisor, bool store, bool fetch);
+
+ // translate a virtual address to a physical address
+ void* translate(reg_t addr, reg_t bytes, bool store, bool fetch)
+ __attribute__((always_inline))
{
- check_align(addr, size, store, fetch);
- check_bounds(addr, size, store, fetch);
+ reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
+ reg_t expected_tag = addr >> PGSHIFT;
+ reg_t* tags = fetch ? tlb_insn_tag : store ? tlb_store_tag :tlb_load_tag;
+ reg_t tag = tags[idx];
+ void* data = tlb_data[idx] + addr;
+
+ if (unlikely(addr & (bytes-1)))
+ store ? throw trap_store_address_misaligned(addr) :
+ fetch ? throw trap_instruction_address_misaligned(addr) :
+ throw trap_load_address_misaligned(addr);
+
+ if (likely(tag == expected_tag))
+ return data;
+
+ return refill_tlb(addr, bytes, store, fetch);
}
friend class processor_t;
};
+
+#endif
projects / riscv-isa-sim.git / blobdiff