Merge branch 'master' of /project/eecs/parlab/git/projects/riscv
[riscv-isa-sim.git] / riscv / processor.cc
index e04f4985d74ceea9633b9f0f29335ecad78e70f6..271afbf0115652af627073b693c1d1858a4f3a5c 100644 (file)
@@ -21,6 +21,8 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   tid = 0;
   pcr_k0 = 0;
   pcr_k1 = 0;
+  tohost = 0;
+  fromhost = 0;
   count = 0;
   compare = 0;
   interrupts_pending = 0;