msv.state_size = 1;
ssv.state_size = 1;
usv.state_size = 3;
+ // VL and MVL all 0
+ msv.vl = msv.mvl = 0;
+ ssv.vl = ssv.mvl = 0;
+ usv.vl = usv.mvl = 0;
+ // SUBVL all 1, including in xesvstate
+ msv.subvl = 1;
+ ssv.subvl = 1;
+ usv.subvl = 1;
+ mesvstate = sesvstate = 0;
#endif
}
return get_usv();
}
-sv_shape_t* state_t::get_shape(reg_t reg)
+sv_shape_t* state_t::get_shape(reg_t reg, bool pred)
{
if (prv == PRV_M || prv == PRV_S || reg == 0) {
return NULL;
}
for (int i = 0; i < 3; i++) {
- if (remap[i].regidx == reg) {
+ if (remap[i].regidx == reg && remap[i].pred == pred) {
return &shape[i];
}
}
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
reg_t deleg = state.medeleg;
+ reg_t svstate = get_csr(CSR_SV_STATE);
bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
if (interrupt)
deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
state.pc = state.stvec;
state.scause = t.cause();
state.sepc = epc;
+ state.sesvstate = svstate;
state.stval = t.get_tval();
reg_t s = state.mstatus;
reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
state.pc = (state.mtvec & ~(reg_t)1) + vector;
state.mepc = epc;
+ state.mesvstate = svstate;
state.mcause = t.cause();
state.mtval = t.get_tval();
r->regidx = c->b.regidx;
r->zero = c->b.zero;
r->inv = c->b.inv;
- r->packed = c->b.packed;
+ r->ffirst = c->b.ffirst;
r->active = true;
fprintf(stderr, "setting PREDCFG %d type:%d zero:%d %d %d\n",
i, c->b.type, r->zero, (int)idx, (int)r->regidx);
}
}
-void processor_t::set_csr(int which, reg_t val)
+reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
{
+ reg_t old_val = get_csr(which);
val = _zext_xlen(val);
reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
| ((ext != NULL) << IRQ_COP);
switch (which)
{
#ifdef SPIKE_SIMPLEV
- case CSR_USVMVL:
- state.sv().mvl = std::min(val, (uint64_t)64); // limited to XLEN width
+ case CSR_SV_MVL:
+ state.sv().mvl = std::min(val+1, (uint64_t)64); // limited to XLEN width
+ old_val = state.sv().mvl - 1;
// TODO XXX throw exception if val == 0
fprintf(stderr, "set MVL %lx\n", state.sv().mvl);
break;
- case CSR_USVSTATE:
+ case CSR_SV_STATE:
{
// bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
- set_csr(CSR_USVMVL, get_field(val, SV_STATE_VL )+1);
- set_csr(CSR_USVVL , get_field(val, SV_STATE_MVL)+1);
+ set_csr(CSR_SV_MVL, get_field(val, SV_STATE_VL ));
+ set_csr(CSR_SV_VL , get_field(val, SV_STATE_MVL));
+ set_csr(CSR_SV_SUBVL , get_field(val, SV_STATE_SUBVL)+1);
+ // decode (and limit) src/dest VL offsets
reg_t srcoffs = get_field(val, SV_STATE_SRCOFFS);
reg_t destoffs = get_field(val, SV_STATE_DESTOFFS);
state.sv().srcoffs = std::min(srcoffs , state.sv().vl-1);
state.sv().destoffs = std::min(destoffs, state.sv().vl-1);
+ // decode (and limit) src/dest SUBVL offsets
+ reg_t subdestoffs = get_field(val, SV_STATE_DSVOFFS);
+ state.sv().dsvoffs = std::min(subdestoffs, state.sv().subvl-1);
+ //int state_bank = get_field(val, SV_STATE_BANK);
+ //int state_size = get_field(val, SV_STATE_SIZE);
+ //set_csr(CSR_USVCFG, state_bank | (state_size << 3));
+ break;
+ }
+ case CSR_SV_CFG:
+ {
int old_bank = state.sv().state_bank;
int old_size = state.sv().state_size;
- state.sv().state_bank = get_field(val, SV_STATE_BANK);
- state.sv().state_size = get_field(val, SV_STATE_SIZE);
+ state.sv().state_bank = get_field(val, SV_CFG_BANK);
+ state.sv().state_size = get_field(val, SV_CFG_SIZE);
if (old_bank != state.sv().state_bank ||
old_size != state.sv().state_size)
{
}
break;
}
- case CSR_USVVL:
- state.sv().vl = std::min(state.sv().mvl, val);
+ case CSR_SV_SUBVL:
+ state.sv().subvl = std::max(1, std::min(4, (int)val));
+ old_val = state.sv().subvl;
+ // TODO XXX throw exception if val attempted to be set == 0
+ fprintf(stderr, "set SUBVL %lx\n", state.sv().subvl);
+ break;
+ case CSR_SV_VL:
+ state.sv().vl = std::min(state.sv().mvl, val + 1);
+ old_val = state.sv().mvl - 1;
// TODO XXX throw exception if val == 0
fprintf(stderr, "set VL %lx\n", state.sv().vl);
break;
- case CSR_SVREGCFG0:
- case CSR_SVREGCFG1:
- case CSR_SVREGCFG2:
- case CSR_SVREGCFG3:
- case CSR_SVREGCFG4:
- case CSR_SVREGCFG5:
- case CSR_SVREGCFG6:
- case CSR_SVREGCFG7:
+ case CSR_SVREGTOP:
+ case CSR_SVREGBOT:
{
+ bool top = (which == CSR_SVREGTOP);
uint64_t v = (uint64_t)val;
- // identify which (pair) of SV config CAM registers are being set
- int tbidx = (which - CSR_SVREGCFG0) * 2;
- fprintf(stderr, "set REGCFG %d %lx\n", tbidx, v);
- // lower 16 bits go into even, upper into odd...
- state.sv().sv_csrs[tbidx].u = get_field(v, 0xffffUL);
- state.sv().sv_csrs[tbidx+1].u = get_field(v, 0xffffUL<<16);
- int clroffset = 2;
- if (xlen == 64)
- {
- state.sv().sv_csrs[tbidx+2].u = get_field(v, 0xffffUL<<32);
- state.sv().sv_csrs[tbidx+3].u = get_field(v, 0xffffUL<<48);
- clroffset = 4;
+ fprintf(stderr, "set SVREG %d %lx\n", top, v);
+ int start = 0;
+ int end = 0;
+ state.get_csr_start_end(start, end);
+ uint64_t res_old = 0;
+ int num_entries = val & 0xf;
+ int max_xlen_entries = (xlen == 64) ? 4 : 2;
+ if (!imm_mode) {
+ num_entries = max_xlen_entries;
}
- // clear out all CSRs above the one(s) being set: this ensures that
- // when it comes to context-switching, it's clear what needs to be saved
- for (int i = tbidx+clroffset; i < 16; i++)
- {
- fprintf(stderr, "clr REGCFG %d\n", i);
- state.sv().sv_csrs[i].u = 0;
+ // read 2 16-bit entries for RV32, 4 16-bit entries for RV64
+ int popidx = 0;
+ for (int i = 0; i < num_entries; i++) {
+ uint64_t svcfg = 0;
+ if (!imm_mode) {
+ uint64_t mask = 0xffffUL << (i*16UL);
+ svcfg = get_field(v, mask);
+ fprintf(stderr, "SVREG mask %lx cfg %lx\n", mask, svcfg);
+ if (!svcfg && i > 0) {
+ break;
+ }
+ }
+ // see regpush on how this works.
+ uint64_t res = state.sv().regpush(svcfg, end, top);
+ if (res != 0) {
+ res_old |= res << (popidx * 16UL);
+ popidx += 1;
+ if (popidx == max_xlen_entries) {
+ break;
+ }
+ }
}
+ old_val = res_old;
state.sv_csr_reg_unpack();
break;
}
state.remap[0].regidx = get_field(val, SV_REMAP_REGIDX0);
state.remap[1].regidx = get_field(val, SV_REMAP_REGIDX1);
state.remap[2].regidx = get_field(val, SV_REMAP_REGIDX2);
+ state.remap[0].pred = get_field(val, SV_REMAP_PRED0);
+ state.remap[1].pred = get_field(val, SV_REMAP_PRED1);
+ state.remap[2].pred = get_field(val, SV_REMAP_PRED2);
state.remap[0].shape = get_field(val, SV_REMAP_SHAPE0);
state.remap[1].shape = get_field(val, SV_REMAP_SHAPE1);
state.remap[2].shape = get_field(val, SV_REMAP_SHAPE2);
break;
}
case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
+ case CSR_SESVSTATE: state.sesvstate = val; break;
case CSR_STVEC: state.stvec = val >> 2 << 2; break;
case CSR_SSCRATCH: state.sscratch = val; break;
case CSR_SCAUSE: state.scause = val; break;
case CSR_STVAL: state.stval = val; break;
case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
+ case CSR_MESVSTATE: state.mesvstate = val; break;
case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
state.dscratch = val;
break;
}
+ return old_val;
}
reg_t processor_t::get_csr(int which)
switch (which)
{
#ifdef SPIKE_SIMPLEV
- case CSR_USVVL:
+ case CSR_SV_VL:
return state.sv().vl;
- case CSR_USVSTATE:
- return (state.sv().vl-1) | ((state.sv().mvl-1)<<6) |
- (state.sv().srcoffs<<12) | (state.sv().destoffs<<18) |
- (state.sv().state_bank<<24) | (state.sv().state_size<<26);
- case CSR_USVMVL:
+ case CSR_SV_CFG:
+ return (state.sv().state_bank) | (state.sv().state_size<<3);
+ case CSR_SV_STATE:
+ fprintf(stderr, "get CSR_SV_STATE vl %ld mvl %ld subvl %ld\n",
+ state.sv().vl,
+ state.sv().mvl,
+ state.sv().subvl);
+ return ((std::max((int)state.sv().vl, 1))-1) |
+ ((std::max((int)state.sv().mvl, 1)-1)<<6) |
+ (state.sv().srcoffs<<12) |
+ (state.sv().destoffs<<18) |
+ ((std::max((int)state.sv().subvl, 1)-1)<<24) |
+ (state.sv().dsvoffs<<26);
+ case CSR_SV_MVL:
return state.sv().mvl;
- case CSR_SVREGCFG0:
- case CSR_SVREGCFG1:
- case CSR_SVREGCFG2:
- case CSR_SVREGCFG3:
- case CSR_SVREGCFG4:
- case CSR_SVREGCFG5:
- case CSR_SVREGCFG6:
- case CSR_SVREGCFG7:
+ case CSR_SV_SUBVL:
+ return state.sv().subvl;
+ case CSR_SVREGTOP:
+ case CSR_SVREGBOT:
return 0;// XXX TODO: return correct entry
case CSR_SVPREDCFG0:
case CSR_SVPREDCFG1:
case CSR_SIP: return state.mip & state.mideleg;
case CSR_SIE: return state.mie & state.mideleg;
case CSR_SEPC: return state.sepc & pc_alignment_mask();
+ case CSR_SESVSTATE: return state.sesvstate;
case CSR_STVAL: return state.stval;
case CSR_STVEC: return state.stvec;
case CSR_SCAUSE:
case CSR_MIP: return state.mip;
case CSR_MIE: return state.mie;
case CSR_MEPC: return state.mepc & pc_alignment_mask();
+ case CSR_MESVSTATE: return state.mesvstate;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MTVAL: return state.mtval;
projects / riscv-isa-sim.git / blobdiff