Fixed masking/casting logic in commit log printf.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 956b2d3a4ed1e4d0c41abb79b2a496893bbedf28..0a344465df6b39ddf981e22b8c28f3ea4f67eeb2 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -7,7 +7,6 @@
 #include "sim.h"
 #include "htif.h"
 #include "disasm.h"
-#include "icache.h"
 #include <cinttypes>
 #include <cmath>
 #include <cstdlib>
@@ -124,19 +123,20 @@ void processor_t::take_interrupt()
       throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
 }
 
-static void commit_log(state_t* state, insn_t insn)
+static void commit_log(state_t* state, reg_t pc, insn_t insn)
 {
 #ifdef RISCV_ENABLE_COMMITLOG
   if (state->sr & SR_EI) {
+    uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
     if (state->log_reg_write.addr) {
-      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx32 ") %c%2u 0x%016" PRIx64 "\n",
-              state->pc, insn.bits(),
+      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
+              pc,
+              insn.bits() & mask,
               state->log_reg_write.addr & 1 ? 'f' : 'x',
-              state->log_reg_write.addr >> 1, state->log_reg_write.data);
-    }
-    else {
-      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx32 ")\n",
-              state->pc, insn.bits());
+              state->log_reg_write.addr >> 1,
+              state->log_reg_write.data);
+    } else {
+      fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
     }
   }
   state->log_reg_write.addr = 0;
@@ -153,8 +153,8 @@ inline void processor_t::update_histogram(size_t pc)
 
 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 {
-  reg_t npc = fetch.func(p, fetch.insn.insn, pc);
-  commit_log(p->get_state(), fetch.insn.insn);
+  reg_t npc = fetch.func(p, fetch.insn, pc);
+  commit_log(p->get_state(), pc, fetch.insn);
   p->update_histogram(pc);
   return npc;
 }
@@ -192,13 +192,13 @@ void processor_t::step(size_t n)
       while (instret++ < n)
       {
         insn_fetch_t fetch = mmu->load_insn(pc);
-        disasm(fetch.insn.insn);
+        disasm(fetch.insn);
         pc = execute_insn(this, pc, fetch);
       }
     }
     else while (instret < n)
     {
-      size_t idx = (pc / sizeof(insn_t)) % ICACHE_SIZE;
+      size_t idx = _mmu->icache_index(pc);
       auto ic_entry = _mmu->access_icache(pc);
 
       #define ICACHE_ACCESS(idx) { \
@@ -206,12 +206,12 @@ void processor_t::step(size_t n)
         ic_entry++; \
         pc = execute_insn(this, pc, fetch); \
         instret++; \
-        if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != pc)) break; \
+        if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
+        if (unlikely(ic_entry->tag != pc)) break; \
       }
 
-      switch (idx)
-      {
-        ICACHE_SWITCH; // auto-generated into icache.h
+      switch (idx) {
+        #include "icache.h"
       }
     }
   }
@@ -251,9 +251,9 @@ void processor_t::deliver_ipi()
 
 void processor_t::disasm(insn_t insn)
 {
-  // the disassembler is stateless, so we share it
-  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
-          id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
+  uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
+  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+          id, state.pc, bits, disassembler->disassemble(insn).c_str());
 }
 
 void processor_t::set_pcr(int which, reg_t val)