#include "sim.h"
#include "htif.h"
#include "disasm.h"
-#include "icache.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
#include <stdexcept>
#include <algorithm>
+#undef STATE
+#define STATE state
+
processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
: sim(_sim), mmu(_mmu), ext(NULL), disassembler(new disassembler_t),
- id(_id), run(false), debug(false)
+ id(_id), run(false), debug(false), serialized(false)
{
reset(true);
mmu->set_processor(this);
processor_t::~processor_t()
{
+#ifdef RISCV_ENABLE_HISTOGRAM
+ if (histogram_enabled)
+ {
+ fprintf(stderr, "PC Histogram size:%lu\n", pc_histogram.size());
+ for(auto iterator = pc_histogram.begin(); iterator != pc_histogram.end(); ++iterator) {
+ fprintf(stderr, "%0lx %lu\n", (iterator->first << 2), iterator->second);
+ }
+ }
+#endif
+
delete disassembler;
}
ext->set_debug(value);
}
+void processor_t::set_histogram(bool value)
+{
+ histogram_enabled = value;
+}
+
void processor_t::reset(bool value)
{
if (run == !value)
ext->reset(); // reset the extension
}
+struct serialize_t {};
+
+void processor_t::serialize()
+{
+ if (serialized)
+ serialized = false;
+ else
+ serialized = true, throw serialize_t();
+}
+
void processor_t::take_interrupt()
{
- uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
- interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
+ int irqs = ((state.sr & SR_IP) >> SR_IP_SHIFT) & (state.sr >> SR_IM_SHIFT);
+ if (likely(!irqs) || likely(!(state.sr & SR_EI)))
+ return;
- if (interrupts && (state.sr & SR_EI))
- for (int i = 0; ; i++, interrupts >>= 1)
- if (interrupts & 1)
- throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
+ for (int i = 0; ; i++)
+ if ((irqs >> i) & 1)
+ throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
}
-static void commit_log(state_t* state, insn_t insn)
+static void commit_log(state_t* state, reg_t pc, insn_t insn)
{
#ifdef RISCV_ENABLE_COMMITLOG
- if (!(state->sr & SR_S)) {
- fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", state->pc, insn.bits());
- if (state->log_reg_write.addr)
- fprintf(stderr, "%c%02u 0x%016" PRIx64, state->log_reg_write.addr & 1 ? 'f' : 'x',
- state->log_reg_write.addr >> 1, state->log_reg_write.data);
- state->log_reg_write.addr = 0;
+ if (state->sr & SR_EI) {
+ uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
+ if (state->log_reg_write.addr) {
+ fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
+ pc,
+ insn.bits() & mask,
+ state->log_reg_write.addr & 1 ? 'f' : 'x',
+ state->log_reg_write.addr >> 1,
+ state->log_reg_write.data);
+ } else {
+ fprintf(stderr, "0x%016" PRIx64 " (0x%08" PRIx64 ")\n", pc, insn.bits() & mask);
+ }
}
+ state->log_reg_write.addr = 0;
#endif
}
-void processor_t::step(size_t n)
+inline void processor_t::update_histogram(size_t pc)
{
- if(!run)
- return;
+#ifdef RISCV_ENABLE_HISTOGRAM
+ size_t idx = pc >> 2;
+ pc_histogram[idx]++;
+#endif
+}
+static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
+{
+ reg_t npc = fetch.func(p, fetch.insn, pc);
+ commit_log(p->get_state(), pc, fetch.insn);
+ p->update_histogram(pc);
+ return npc;
+}
+
+static void update_timer(state_t* state, size_t instret)
+{
+ uint64_t count0 = (uint64_t)(uint32_t)state->count;
+ state->count += instret;
+ uint64_t before = count0 - state->compare;
+ if (int64_t(before ^ (before + instret)) < 0)
+ state->sr |= (1 << (IRQ_TIMER + SR_IP_SHIFT));
+}
+
+static size_t next_timer(state_t* state)
+{
+ return state->compare - (uint32_t)state->count;
+}
+
+void processor_t::step(size_t n)
+{
+ size_t instret = 0;
+ reg_t pc = state.pc;
mmu_t* _mmu = mmu;
- auto count32 = decltype(state.compare)(state.count);
- bool count_le_compare = count32 <= state.compare;
- n = std::min(n, size_t(state.compare - count32) | 1);
+
+ if (unlikely(!run || !n))
+ return;
+ n = std::min(n, next_timer(&state) | 1U);
try
{
take_interrupt();
- if (debug) // print out instructions as we go
+ if (unlikely(debug))
{
- for (size_t i = 0; i < n; state.count++, i++)
+ while (instret++ < n)
{
- insn_fetch_t fetch = mmu->load_insn(state.pc);
- disasm(fetch.insn.insn);
- commit_log(&state, fetch.insn.insn);
- state.pc = fetch.func(this, fetch.insn.insn, state.pc);
+ insn_fetch_t fetch = mmu->load_insn(pc);
+ disasm(fetch.insn);
+ pc = execute_insn(this, pc, fetch);
}
}
- else while (n > 0)
+ else while (instret < n)
{
- size_t idx = (state.pc / sizeof(insn_t)) % ICACHE_SIZE;
- auto ic_entry = _mmu->access_icache(state.pc), ic_entry_init = ic_entry;
+ size_t idx = _mmu->icache_index(pc);
+ auto ic_entry = _mmu->access_icache(pc);
#define ICACHE_ACCESS(idx) { \
- insn_t insn = ic_entry->data.insn.insn; \
- insn_func_t func = ic_entry->data.func; \
+ insn_fetch_t fetch = ic_entry->data; \
ic_entry++; \
- reg_t pc = func(this, insn, state.pc); \
- commit_log(&state, insn); \
- state.pc = pc; \
- if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != state.pc)) break; \
+ pc = execute_insn(this, pc, fetch); \
+ instret++; \
+ if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
+ if (unlikely(ic_entry->tag != pc)) break; \
}
- switch (idx)
- {
- ICACHE_SWITCH; // auto-generated into icache.h
+ switch (idx) {
+ #include "icache.h"
}
-
- size_t i = ic_entry - ic_entry_init;
- state.count += i;
- if (i >= n)
- break;
- n -= i;
}
}
catch(trap_t& t)
{
- take_trap(t);
+ pc = take_trap(t, pc);
}
+ catch(serialize_t& s) {}
- bool count_ge_compare =
- uint64_t(n) + decltype(state.compare)(state.count) >= state.compare;
- if (count_le_compare && count_ge_compare)
- set_interrupt(IRQ_TIMER, true);
+ state.pc = pc;
+ update_timer(&state, instret);
}
-void processor_t::take_trap(trap_t& t)
+reg_t processor_t::take_trap(trap_t& t, reg_t epc)
{
if (debug)
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
- id, t.name(), state.pc);
+ id, t.name(), epc);
// switch to supervisor, set previous supervisor bit, disable interrupts
set_pcr(CSR_STATUS, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
yield_load_reservation();
state.cause = t.cause();
- state.epc = state.pc;
- state.pc = state.evec;
-
+ state.epc = epc;
t.side_effects(&state); // might set badvaddr etc.
+ return state.evec;
}
void processor_t::deliver_ipi()
void processor_t::disasm(insn_t insn)
{
- // the disassembler is stateless, so we share it
- fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
- id, state.pc, insn.bits(), disassembler->disassemble(insn).c_str());
+ uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx64 ") %s\n",
+ id, state.pc, bits, disassembler->disassemble(insn).c_str());
}
-reg_t processor_t::set_pcr(int which, reg_t val)
+void processor_t::set_pcr(int which, reg_t val)
{
- reg_t old_pcr = get_pcr(which);
-
switch (which)
{
case CSR_FFLAGS:
state.count = (val << 32) | (uint32_t)state.count;
break;
case CSR_COMPARE:
+ serialize();
set_interrupt(IRQ_TIMER, false);
state.compare = val;
break;
set_fromhost(val);
break;
}
-
- return old_pcr;
}
void processor_t::set_fromhost(reg_t val)
switch (which)
{
case CSR_FFLAGS:
+ require_fp;
return state.fflags;
case CSR_FRM:
+ require_fp;
return state.frm;
case CSR_FCSR:
+ require_fp;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
case CSR_STATUS:
return state.sr;
case CSR_TIME:
case CSR_INSTRET:
case CSR_COUNT:
+ serialize();
return state.count;
case CSR_CYCLEH:
case CSR_TIMEH:
case CSR_COUNTH:
if (rv64)
break;
+ serialize();
return state.count >> 32;
case CSR_COMPARE:
return state.compare;
case CSR_FROMHOST:
sim->get_htif()->tick(); // not necessary, but faster
return state.fromhost;
+ case CSR_UARCH0:
+ case CSR_UARCH1:
+ case CSR_UARCH2:
+ case CSR_UARCH3:
+ case CSR_UARCH4:
+ case CSR_UARCH5:
+ case CSR_UARCH6:
+ case CSR_UARCH7:
+ case CSR_UARCH8:
+ case CSR_UARCH9:
+ case CSR_UARCH10:
+ case CSR_UARCH11:
+ case CSR_UARCH12:
+ case CSR_UARCH13:
+ case CSR_UARCH14:
+ case CSR_UARCH15:
+ return 0;
}
throw trap_illegal_instruction();
}
projects / riscv-isa-sim.git / blobdiff