#include "config.h"
#include "sim.h"
#include "mmu.h"
-#include "htif.h"
#include "disasm.h"
#include "gdbserver.h"
#include <cinttypes>
#undef STATE
#define STATE state
-processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
+processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
+ bool halt_on_reset)
: debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
- id(id), run(false)
+ id(id), halt_on_reset(halt_on_reset)
{
parse_isa_string(isa);
mmu = new mmu_t(sim, this);
- reset(true);
+ reset();
register_base_instructions();
}
#endif
}
-void processor_t::reset(bool value)
+void processor_t::reset()
{
- if (run == !value)
- return;
- run = !value;
-
state.reset();
+ state.dcsr.halt = halt_on_reset;
+ halt_on_reset = false;
set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
void processor_t::enter_debug_mode(uint8_t cause)
{
- fprintf(stderr, "enter_debug_mode(%d), mstatus=0x%lx, prv=0x%lx\n", cause, state.mstatus, state.prv);
state.dcsr.cause = cause;
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
state.pc = DEBUG_ROM_START;
- debug = true; // TODO
+ //debug = true; // TODO
}
void processor_t::take_trap(trap_t& t, reg_t epc)
t.get_badaddr());
}
- if (t.cause() == CAUSE_BREAKPOINT &&
- sim->gdbserver && sim->gdbserver->connected()) {
+ if (t.cause() == CAUSE_BREAKPOINT && (
+ (state.prv == PRV_M && state.dcsr.ebreakm) ||
+ (state.prv == PRV_H && state.dcsr.ebreakh) ||
+ (state.prv == PRV_S && state.dcsr.ebreaks) ||
+ (state.prv == PRV_U && state.dcsr.ebreaku))) {
enter_debug_mode(DCSR_CAUSE_SWBP);
return;
}
+ if (state.dcsr.cause) {
+ state.pc = DEBUG_ROM_EXCEPTION;
+ return;
+ }
+
// by default, trap to M-mode, unless delegated to S-mode
reg_t bit = t.cause();
reg_t deleg = state.medeleg;
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
- if (state.dcsr.cause) {
- state.pc = DEBUG_ROM_EXCEPTION;
- } else {
- state.pc = state.mtvec;
- }
- state.mcause = t.cause();
+ state.pc = state.mtvec;
state.mepc = epc;
+ state.mcause = t.cause();
if (t.has_badaddr())
state.mbadaddr = t.get_badaddr();
return vm == VM_MBARE;
}
+int processor_t::paddr_bits()
+{
+ assert(xlen == max_xlen);
+ return max_xlen == 64 ? 50 : 34;
+}
+
void processor_t::set_csr(int which, reg_t val)
{
- fprintf(stderr, "set_csr(0x%x, 0x%lx)\n", which, val);
val = zext_xlen(val);
reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
case CSR_SIE:
return set_csr(CSR_MIE,
(state.mie & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SPTBR: {
+ // upper bits of sptbr are the ASID; we only support ASID = 0
+ state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
+ break;
+ }
case CSR_SEPC: state.sepc = val; break;
case CSR_STVEC: state.stvec = val >> 2 << 2; break;
- case CSR_SPTBR: state.sptbr = val; break;
case CSR_SSCRATCH: state.sscratch = val; break;
case CSR_SCAUSE: state.scause = val; break;
case CSR_SBADADDR: state.sbadaddr = val; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
- case DCSR_ADDRESS:
- // TODO: Use get_field style
- state.dcsr.prv = (val & DCSR_PRV_MASK) >> DCSR_PRV_OFFSET;
- state.dcsr.step = (val & DCSR_STEP_MASK) >> DCSR_STEP_OFFSET;
+ case CSR_DCSR:
+ state.dcsr.prv = get_field(val, DCSR_PRV);
+ state.dcsr.step = get_field(val, DCSR_STEP);
// TODO: ndreset and fullreset
- state.dcsr.ebreakm = (val & DCSR_EBREAKM_MASK) >> DCSR_EBREAKM_OFFSET;
- state.dcsr.ebreakh = (val & DCSR_EBREAKH_MASK) >> DCSR_EBREAKH_OFFSET;
- state.dcsr.ebreaks = (val & DCSR_EBREAKS_MASK) >> DCSR_EBREAKS_OFFSET;
- state.dcsr.ebreaku = (val & DCSR_EBREAKU_MASK) >> DCSR_EBREAKU_OFFSET;
- state.dcsr.halt = (val & DCSR_HALT_MASK) >> DCSR_HALT_OFFSET;
+ state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
+ state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
+ state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
+ state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
+ state.dcsr.halt = get_field(val, DCSR_HALT);
break;
- case DPC_ADDRESS:
+ case CSR_DPC:
state.dpc = val;
break;
- case DSCRATCH_ADDRESS:
+ case CSR_DSCRATCH:
state.dscratch = val;
break;
}
return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
return state.scause;
case CSR_SPTBR: return state.sptbr;
- case CSR_SASID: return 0;
case CSR_SSCRATCH: return state.sscratch;
case CSR_MSTATUS: return state.mstatus;
case CSR_MIP: return state.mip;
case CSR_MTVEC: return state.mtvec;
case CSR_MEDELEG: return state.medeleg;
case CSR_MIDELEG: return state.mideleg;
- case DCSR_ADDRESS:
+ case CSR_TDRSELECT: return 0;
+ case CSR_DCSR:
{
- uint32_t value =
- (1 << DCSR_XDEBUGVER_OFFSET) |
- (0 << DCSR_HWBPCOUNT_OFFSET) |
- (0 << DCSR_NDRESET_OFFSET) |
- (0 << DCSR_FULLRESET_OFFSET) |
- (state.dcsr.prv << DCSR_PRV_OFFSET) |
- (state.dcsr.step << DCSR_STEP_OFFSET) |
- (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
- (0 << DCSR_STOPCYCLE_OFFSET) |
- (0 << DCSR_STOPTIME_OFFSET) |
- (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |
- (state.dcsr.ebreakh << DCSR_EBREAKH_OFFSET) |
- (state.dcsr.ebreaks << DCSR_EBREAKS_OFFSET) |
- (state.dcsr.ebreaku << DCSR_EBREAKU_OFFSET) |
- (state.dcsr.halt << DCSR_HALT_OFFSET) |
- (state.dcsr.cause << DCSR_CAUSE_OFFSET);
- return value;
+ uint32_t v = 0;
+ v = set_field(v, DCSR_XDEBUGVER, 1);
+ v = set_field(v, DCSR_HWBPCOUNT, 0);
+ v = set_field(v, DCSR_NDRESET, 0);
+ v = set_field(v, DCSR_FULLRESET, 0);
+ v = set_field(v, DCSR_PRV, state.dcsr.prv);
+ v = set_field(v, DCSR_STEP, state.dcsr.step);
+ v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
+ v = set_field(v, DCSR_STOPCYCLE, 0);
+ v = set_field(v, DCSR_STOPTIME, 0);
+ v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
+ v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
+ v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
+ v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
+ v = set_field(v, DCSR_HALT, state.dcsr.halt);
+ v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
+ return v;
}
- case DPC_ADDRESS:
+ case CSR_DPC:
return state.dpc;
- case DSCRATCH_ADDRESS:
+ case CSR_DSCRATCH:
return state.dscratch;
}
throw trap_illegal_instruction();
projects / riscv-isa-sim.git / blobdiff