#include "common.h"
#include "config.h"
#include "sim.h"
-#include "htif.h"
+#include "mmu.h"
#include "disasm.h"
+#include "gdbserver.h"
#include <cinttypes>
#include <cmath>
#include <cstdlib>
#undef STATE
#define STATE state
-processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id)
- : sim(sim), ext(NULL), disassembler(new disassembler_t),
- id(id), run(false), debug(false)
+processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
+ bool halt_on_reset)
+ : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
+ id(id), halt_on_reset(halt_on_reset)
{
parse_isa_string(isa);
- mmu = new mmu_t(sim->mem, sim->memsz);
- mmu->set_processor(this);
+ mmu = new mmu_t(sim, this);
- reset(true);
+ reset();
register_base_instructions();
}
const char* all_subsets = "imafdc";
max_xlen = 64;
- cpuid = reg_t(2) << 62;
+ isa = reg_t(2) << 62;
if (strncmp(p, "rv32", 4) == 0)
- max_xlen = 32, cpuid = 0, p += 4;
+ max_xlen = 32, isa = reg_t(1) << 30, p += 4;
else if (strncmp(p, "rv64", 4) == 0)
p += 4;
else if (strncmp(p, "rv", 2) == 0)
bad_isa_string(str);
}
- isa = "rv" + std::to_string(max_xlen) + p;
- cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+ isa_string = "rv" + std::to_string(max_xlen) + p;
+ isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
while (*p) {
- cpuid |= 1L << (*p - 'a');
+ isa |= 1L << (*p - 'a');
if (auto next = strchr(all_subsets, *p)) {
all_subsets = next + 1;
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
+
+ // advertise support for supervisor and user modes
+ isa |= 1L << ('s' - 'a');
+ isa |= 1L << ('u' - 'a');
}
void state_t::reset()
{
memset(this, 0, sizeof(*this));
- mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
- mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_U);
- mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_U);
- pc = DEFAULT_MTVEC + 0x100;
+ prv = PRV_M;
+ pc = DEFAULT_RSTVEC;
+ mtvec = DEFAULT_MTVEC;
load_reservation = -1;
}
#endif
}
-void processor_t::reset(bool value)
+void processor_t::reset()
{
- if (run == !value)
- return;
- run = !value;
-
state.reset();
+ state.dcsr.halt = halt_on_reset;
+ halt_on_reset = false;
set_csr(CSR_MSTATUS, state.mstatus);
if (ext)
throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
}
-void processor_t::take_interrupt()
+static int ctz(reg_t val)
{
- int priv = get_field(state.mstatus, MSTATUS_PRV);
- int ie = get_field(state.mstatus, MSTATUS_IE);
- reg_t interrupts = state.mie & state.mip;
+ int res = 0;
+ if (val)
+ while ((val & 1) == 0)
+ val >>= 1, res++;
+ return res;
+}
- if (priv < PRV_M || (priv == PRV_M && ie)) {
- if (interrupts & MIP_MSIP)
- raise_interrupt(IRQ_SOFT);
+void processor_t::take_interrupt()
+{
+ reg_t pending_interrupts = state.mip & state.mie;
- if (interrupts & MIP_MTIP)
- raise_interrupt(IRQ_TIMER);
+ reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
+ reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
+ reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
- if (state.fromhost != 0)
- raise_interrupt(IRQ_HOST);
- }
+ reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
+ reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
+ enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
- if (priv < PRV_S || (priv == PRV_S && ie)) {
- if (interrupts & MIP_SSIP)
- raise_interrupt(IRQ_SOFT);
-
- if (interrupts & MIP_STIP)
- raise_interrupt(IRQ_TIMER);
- }
+ if (enabled_interrupts)
+ raise_interrupt(ctz(enabled_interrupts));
}
-void processor_t::check_timer()
+static bool validate_priv(reg_t priv)
{
- if (sim->rtc >= state.mtimecmp)
- state.mip |= MIP_MTIP;
+ return priv == PRV_U || priv == PRV_S || priv == PRV_M;
}
-void processor_t::push_privilege_stack()
+void processor_t::set_privilege(reg_t prv)
{
- reg_t s = state.mstatus;
- s = set_field(s, MSTATUS_PRV2, get_field(state.mstatus, MSTATUS_PRV1));
- s = set_field(s, MSTATUS_IE2, get_field(state.mstatus, MSTATUS_IE1));
- s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
- s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
- s = set_field(s, MSTATUS_PRV, PRV_M);
- s = set_field(s, MSTATUS_MPRV, 0);
- s = set_field(s, MSTATUS_IE, 0);
- set_csr(CSR_MSTATUS, s);
+ assert(validate_priv(prv));
+ mmu->flush_tlb();
+ state.prv = prv;
}
-void processor_t::pop_privilege_stack()
+void processor_t::enter_debug_mode(uint8_t cause)
{
- reg_t s = state.mstatus;
- s = set_field(s, MSTATUS_PRV, get_field(state.mstatus, MSTATUS_PRV1));
- s = set_field(s, MSTATUS_IE, get_field(state.mstatus, MSTATUS_IE1));
- s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV2));
- s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE2));
- s = set_field(s, MSTATUS_PRV2, PRV_U);
- s = set_field(s, MSTATUS_IE2, 1);
- set_csr(CSR_MSTATUS, s);
+ state.dcsr.cause = cause;
+ state.dcsr.prv = state.prv;
+ set_privilege(PRV_M);
+ state.dpc = state.pc;
+ state.pc = DEBUG_ROM_START;
+ //debug = true; // TODO
}
void processor_t::take_trap(trap_t& t, reg_t epc)
{
- if (debug)
+ if (debug) {
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
+ if (t.has_badaddr())
+ fprintf(stderr, "core %3d: badaddr 0x%016" PRIx64 "\n", id,
+ t.get_badaddr());
+ }
+
+ if (t.cause() == CAUSE_BREAKPOINT && (
+ (state.prv == PRV_M && state.dcsr.ebreakm) ||
+ (state.prv == PRV_H && state.dcsr.ebreakh) ||
+ (state.prv == PRV_S && state.dcsr.ebreaks) ||
+ (state.prv == PRV_U && state.dcsr.ebreaku))) {
+ enter_debug_mode(DCSR_CAUSE_SWBP);
+ return;
+ }
+
+ if (state.dcsr.cause) {
+ state.pc = DEBUG_ROM_EXCEPTION;
+ return;
+ }
+
+ // by default, trap to M-mode, unless delegated to S-mode
+ reg_t bit = t.cause();
+ reg_t deleg = state.medeleg;
+ if (bit & ((reg_t)1 << (max_xlen-1)))
+ deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
+ if (state.prv <= PRV_S && bit < max_xlen && ((deleg >> bit) & 1)) {
+ // handle the trap in S-mode
+ state.pc = state.stvec;
+ state.scause = t.cause();
+ state.sepc = epc;
+ if (t.has_badaddr())
+ state.sbadaddr = t.get_badaddr();
+
+ reg_t s = state.mstatus;
+ s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_UIE << state.prv));
+ s = set_field(s, MSTATUS_SPP, state.prv);
+ s = set_field(s, MSTATUS_SIE, 0);
+ set_csr(CSR_MSTATUS, s);
+ set_privilege(PRV_S);
+ } else {
+ state.pc = state.mtvec;
+ state.mepc = epc;
+ state.mcause = t.cause();
+ if (t.has_badaddr())
+ state.mbadaddr = t.get_badaddr();
+
+ reg_t s = state.mstatus;
+ s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_UIE << state.prv));
+ s = set_field(s, MSTATUS_MPP, state.prv);
+ s = set_field(s, MSTATUS_MIE, 0);
+ set_csr(CSR_MSTATUS, s);
+ set_privilege(PRV_M);
+ }
- state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
- push_privilege_stack();
yield_load_reservation();
- state.mcause = t.cause();
- state.mepc = epc;
- t.side_effects(&state); // might set badvaddr etc.
}
void processor_t::disasm(insn_t insn)
id, state.pc, bits, disassembler->disassemble(insn).c_str());
}
-static bool validate_priv(reg_t priv)
-{
- return priv == PRV_U || priv == PRV_S || priv == PRV_M;
-}
-
static bool validate_vm(int max_xlen, reg_t vm)
{
if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
return vm == VM_MBARE;
}
+int processor_t::paddr_bits()
+{
+ assert(xlen == max_xlen);
+ return max_xlen == 64 ? 50 : 34;
+}
+
void processor_t::set_csr(int which, reg_t val)
{
+ val = zext_xlen(val);
+ reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
+ reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
switch (which)
{
case CSR_FFLAGS:
state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
break;
- case CSR_MTIME:
- case CSR_STIMEW:
- // this implementation ignores writes to MTIME
- break;
- case CSR_MTIMEH:
- case CSR_STIMEHW:
- // this implementation ignores writes to MTIME
- break;
- case CSR_TIMEW:
- val -= sim->rtc;
- if (xlen == 32)
- state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
- else
- state.sutime_delta = val;
- break;
- case CSR_TIMEHW:
- val = ((val << 32) - sim->rtc) >> 32;
- state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
- break;
- case CSR_CYCLEW:
- case CSR_INSTRETW:
- val -= state.minstret;
- if (xlen == 32)
- state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
- else
- state.suinstret_delta = val;
- break;
- case CSR_CYCLEHW:
- case CSR_INSTRETHW:
- val = ((val << 32) - state.minstret) >> 32;
- state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
- break;
case CSR_MSTATUS: {
- if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
+ if ((val ^ state.mstatus) &
+ (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
mmu->flush_tlb();
- reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
- | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
+ reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
+ | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
+ | (ext ? MSTATUS_XS : 0);
if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
mask |= MSTATUS_VM;
- if (validate_priv(get_field(val, MSTATUS_PRV)))
- mask |= MSTATUS_PRV;
- if (validate_priv(get_field(val, MSTATUS_PRV1)))
- mask |= MSTATUS_PRV1;
- if (validate_priv(get_field(val, MSTATUS_PRV2)))
- mask |= MSTATUS_PRV2;
+ if (validate_priv(get_field(val, MSTATUS_MPP)))
+ mask |= MSTATUS_MPP;
state.mstatus = (state.mstatus & ~mask) | (val & mask);
break;
}
case CSR_MIP: {
- reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
+ reg_t mask = MIP_SSIP | MIP_STIP;
state.mip = (state.mip & ~mask) | (val & mask);
break;
}
- case CSR_MIPI: {
- state.mip = set_field(state.mip, MIP_MSIP, val & 1);
+ case CSR_MIE:
+ state.mie = (state.mie & ~all_ints) | (val & all_ints);
break;
- }
- case CSR_MIE: {
- reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP;
- state.mie = (state.mie & ~mask) | (val & mask);
+ case CSR_MIDELEG:
+ state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
+ break;
+ case CSR_MEDELEG: {
+ reg_t mask = 0;
+#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
+#include "encoding.h"
+#undef DECLARE_CAUSE
+ state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
- case CSR_SSTATUS: {
- reg_t ms = state.mstatus;
- ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
- ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
- ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
- ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
- ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
- ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
- return set_csr(CSR_MSTATUS, ms);
- }
- case CSR_SIP: {
- reg_t mask = MIP_SSIP;
- state.mip = (state.mip & ~mask) | (val & mask);
+ case CSR_MUCOUNTEREN:
+ state.mucounteren = val & 7;
+ break;
+ case CSR_MSCOUNTEREN:
+ state.mscounteren = val & 7;
break;
+ case CSR_SSTATUS: {
+ reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+ | SSTATUS_XS | SSTATUS_PUM;
+ return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
}
- case CSR_SIE: {
- reg_t mask = MIP_SSIP | MIP_STIP;
- state.mie = (state.mie & ~mask) | (val & mask);
+ case CSR_SIP:
+ return set_csr(CSR_MIP,
+ (state.mip & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SIE:
+ return set_csr(CSR_MIE,
+ (state.mie & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SPTBR: {
+ // upper bits of sptbr are the ASID; we only support ASID = 0
+ state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
break;
}
case CSR_SEPC: state.sepc = val; break;
case CSR_STVEC: state.stvec = val >> 2 << 2; break;
- case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
case CSR_SSCRATCH: state.sscratch = val; break;
+ case CSR_SCAUSE: state.scause = val; break;
+ case CSR_SBADADDR: state.sbadaddr = val; break;
case CSR_MEPC: state.mepc = val; break;
+ case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
- case CSR_MTIMECMP:
- state.mip &= ~MIP_MTIP;
- state.mtimecmp = val;
+ case CSR_DCSR:
+ state.dcsr.prv = get_field(val, DCSR_PRV);
+ state.dcsr.step = get_field(val, DCSR_STEP);
+ // TODO: ndreset and fullreset
+ state.dcsr.ebreakm = get_field(val, DCSR_EBREAKM);
+ state.dcsr.ebreakh = get_field(val, DCSR_EBREAKH);
+ state.dcsr.ebreaks = get_field(val, DCSR_EBREAKS);
+ state.dcsr.ebreaku = get_field(val, DCSR_EBREAKU);
+ state.dcsr.halt = get_field(val, DCSR_HALT);
+ break;
+ case CSR_DPC:
+ state.dpc = val;
break;
- case CSR_MTOHOST:
- if (state.tohost == 0)
- state.tohost = val;
+ case CSR_DSCRATCH:
+ state.dscratch = val;
break;
- case CSR_MFROMHOST: state.fromhost = val; break;
}
}
if (!supports_extension('F'))
break;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
- case CSR_MTIME:
- case CSR_STIME:
- case CSR_STIMEW:
- return sim->rtc;
- case CSR_MTIMEH:
- case CSR_STIMEH:
- case CSR_STIMEHW:
- return sim->rtc >> 32;
case CSR_TIME:
- case CSR_TIMEW:
- return sim->rtc + state.sutime_delta;
- case CSR_CYCLE:
- case CSR_CYCLEW:
case CSR_INSTRET:
- case CSR_INSTRETW:
- return state.minstret + state.suinstret_delta;
- case CSR_TIMEH:
- case CSR_TIMEHW:
- if (xlen == 64)
- break;
- return (sim->rtc + state.sutime_delta) >> 32;
- case CSR_CYCLEH:
- case CSR_INSTRETH:
- case CSR_CYCLEHW:
- case CSR_INSTRETHW:
- if (xlen == 64)
- break;
- return (state.minstret + state.suinstret_delta) >> 32;
+ case CSR_CYCLE:
+ if ((state.mucounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
+ break;
+ case CSR_STIME:
+ case CSR_SINSTRET:
+ case CSR_SCYCLE:
+ if ((state.mscounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
+ break;
+ case CSR_MUCOUNTEREN: return state.mucounteren;
+ case CSR_MSCOUNTEREN: return state.mscounteren;
+ case CSR_MUCYCLE_DELTA: return 0;
+ case CSR_MUTIME_DELTA: return 0;
+ case CSR_MUINSTRET_DELTA: return 0;
+ case CSR_MSCYCLE_DELTA: return 0;
+ case CSR_MSTIME_DELTA: return 0;
+ case CSR_MSINSTRET_DELTA: return 0;
+ case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MCYCLE: return state.minstret;
+ case CSR_MINSTRET: return state.minstret;
+ case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
+ case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
case CSR_SSTATUS: {
- reg_t ss = 0;
- ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
- ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
- ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
- ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
- ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
- ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
- if (get_field(state.mstatus, MSTATUS64_SD))
- ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
- return ss;
+ reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+ | SSTATUS_XS | SSTATUS_PUM;
+ reg_t sstatus = state.mstatus & mask;
+ if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
+ (sstatus & SSTATUS_XS) == SSTATUS_XS)
+ sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
+ return sstatus;
}
- case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
- case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
+ case CSR_SIP: return state.mip & state.mideleg;
+ case CSR_SIE: return state.mie & state.mideleg;
case CSR_SEPC: return state.sepc;
case CSR_SBADADDR: return state.sbadaddr;
case CSR_STVEC: return state.stvec;
return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
return state.scause;
case CSR_SPTBR: return state.sptbr;
- case CSR_SASID: return 0;
case CSR_SSCRATCH: return state.sscratch;
case CSR_MSTATUS: return state.mstatus;
case CSR_MIP: return state.mip;
- case CSR_MIPI: return 0;
case CSR_MIE: return state.mie;
case CSR_MEPC: return state.mepc;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MBADADDR: return state.mbadaddr;
- case CSR_MTIMECMP: return state.mtimecmp;
- case CSR_MCPUID: return cpuid;
- case CSR_MIMPID: return IMPL_ROCKET;
+ case CSR_MISA: return isa;
+ case CSR_MARCHID: return 0;
+ case CSR_MIMPID: return 0;
+ case CSR_MVENDORID: return 0;
case CSR_MHARTID: return id;
- case CSR_MTVEC: return DEFAULT_MTVEC;
- case CSR_MTDELEG: return 0;
- case CSR_MTOHOST:
- sim->get_htif()->tick(); // not necessary, but faster
- return state.tohost;
- case CSR_MFROMHOST:
- sim->get_htif()->tick(); // not necessary, but faster
- return state.fromhost;
- case CSR_MIOBASE: return sim->memsz;
- case CSR_UARCH0:
- case CSR_UARCH1:
- case CSR_UARCH2:
- case CSR_UARCH3:
- case CSR_UARCH4:
- case CSR_UARCH5:
- case CSR_UARCH6:
- case CSR_UARCH7:
- case CSR_UARCH8:
- case CSR_UARCH9:
- case CSR_UARCH10:
- case CSR_UARCH11:
- case CSR_UARCH12:
- case CSR_UARCH13:
- case CSR_UARCH14:
- case CSR_UARCH15:
- return 0;
+ case CSR_MTVEC: return state.mtvec;
+ case CSR_MEDELEG: return state.medeleg;
+ case CSR_MIDELEG: return state.mideleg;
+ case CSR_TDRSELECT: return 0;
+ case CSR_DCSR:
+ {
+ uint32_t v = 0;
+ v = set_field(v, DCSR_XDEBUGVER, 1);
+ v = set_field(v, DCSR_HWBPCOUNT, 0);
+ v = set_field(v, DCSR_NDRESET, 0);
+ v = set_field(v, DCSR_FULLRESET, 0);
+ v = set_field(v, DCSR_PRV, state.dcsr.prv);
+ v = set_field(v, DCSR_STEP, state.dcsr.step);
+ v = set_field(v, DCSR_DEBUGINT, sim->debug_module.get_interrupt(id));
+ v = set_field(v, DCSR_STOPCYCLE, 0);
+ v = set_field(v, DCSR_STOPTIME, 0);
+ v = set_field(v, DCSR_EBREAKM, state.dcsr.ebreakm);
+ v = set_field(v, DCSR_EBREAKH, state.dcsr.ebreakh);
+ v = set_field(v, DCSR_EBREAKS, state.dcsr.ebreaks);
+ v = set_field(v, DCSR_EBREAKU, state.dcsr.ebreaku);
+ v = set_field(v, DCSR_HALT, state.dcsr.halt);
+ v = set_field(v, DCSR_CAUSE, state.dcsr.cause);
+ return v;
+ }
+ case CSR_DPC:
+ return state.dpc;
+ case CSR_DSCRATCH:
+ return state.dscratch;
}
throw trap_illegal_instruction();
}
bool processor_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
- try {
- auto res = get_csr(addr / (max_xlen / 8));
- memcpy(bytes, &res, len);
- return true;
- } catch (trap_illegal_instruction& t) {
- return false;
- }
+ return false;
}
bool processor_t::store(reg_t addr, size_t len, const uint8_t* bytes)
{
- try {
- reg_t value = 0;
- memcpy(&value, bytes, len);
- set_csr(addr / (max_xlen / 8), value);
- return true;
- } catch (trap_illegal_instruction& t) {
- return false;
+ switch (addr)
+ {
+ case 0:
+ state.mip &= ~MIP_MSIP;
+ if (bytes[0] & 1)
+ state.mip |= MIP_MSIP;
+ return true;
+
+ default:
+ return false;
}
}
projects / riscv-isa-sim.git / blobdiff