Remove legacy HTIF; implement HTIF directly

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f030dfa1f4ac0842dfaa1e895771f41ab3404385..2a31a447d394000762d2587cb8a737d7670fe543 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -6,7 +6,6 @@
 #include "config.h"
 #include "sim.h"
 #include "mmu.h"
-#include "htif.h"
 #include "disasm.h"
 #include "gdbserver.h"
 #include <cinttypes>
@@ -24,13 +23,13 @@
 processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
         bool halt_on_reset)
   : debug(false), sim(sim), ext(NULL), disassembler(new disassembler_t),
-    id(id), run(false), halt_on_reset(halt_on_reset)
+    id(id), halt_on_reset(halt_on_reset)
 {
   parse_isa_string(isa);
 
   mmu = new mmu_t(sim, this);
 
-  reset(true);
+  reset();
 
   register_base_instructions();
 }
@@ -139,12 +138,8 @@ void processor_t::set_histogram(bool value)
 #endif
 }
 
-void processor_t::reset(bool value)
+void processor_t::reset()
 {
-  if (run == !value)
-    return;
-  run = !value;
-
   state.reset();
   state.dcsr.halt = halt_on_reset;
   halt_on_reset = false;
@@ -283,14 +278,10 @@ static bool validate_vm(int max_xlen, reg_t vm)
   return vm == VM_MBARE;
 }
 
-static int paddr_bits(reg_t vm)
+int processor_t::paddr_bits()
 {
-  switch (vm) {
-    case VM_SV32: return 34;
-    case VM_SV39: return 50;
-    case VM_SV48: return 50;
-    default: abort();
-  }
+  assert(xlen == max_xlen);
+  return max_xlen == 64 ? 50 : 34;
 }
 
 void processor_t::set_csr(int which, reg_t val)
@@ -379,8 +370,7 @@ void processor_t::set_csr(int which, reg_t val)
                      (state.mie & ~state.mideleg) | (val & state.mideleg));
     case CSR_SPTBR: {
       // upper bits of sptbr are the ASID; we only support ASID = 0
-      reg_t vm = get_field(state.mstatus, MSTATUS_VM);
-      state.sptbr = val & (((reg_t)1 << (paddr_bits(vm) - PGSHIFT)) - 1);
+      state.sptbr = val & (((reg_t)1 << (paddr_bits() - PGSHIFT)) - 1);
       break;
     }
     case CSR_SEPC: state.sepc = val; break;