Rip out RVC for now

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 5d82937421f6343db790c6ac4ad4c7c4a05ffc7a..3bd4a19a705d9eec701608fc9aefeb61de60053a 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -132,7 +132,7 @@ void processor_t::step(size_t n, bool noisy)
     // execute_insn fetches and executes one instruction
     #define execute_insn(noisy) \
       do { \
-        mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \
+        mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc); \
         if(noisy) disasm(fetch.insn, npc); \
         npc = fetch.func(this, fetch.insn, npc); \
         pc = npc; \