#include "extension.h"
#include "common.h"
#include "config.h"
-#include "sim.h"
+#include "simif.h"
#include "mmu.h"
#include "disasm.h"
#include <cinttypes>
register_base_instructions();
mmu = new mmu_t(sim, this);
+
disassembler = new disassembler_t(max_xlen);
+ if (ext)
+ for (auto disasm_insn : ext->get_disasms())
+ disassembler->add_insn(disasm_insn);
reset();
}
misa = max_isa;
prv = PRV_M;
pc = DEFAULT_RSTVEC;
- load_reservation = -1;
tselect = 0;
for (unsigned int i = 0; i < num_triggers; i++)
mcontrol[i].type = 2;
if (ext)
ext->reset(); // reset the extension
- sim->proc_reset(id);
+ if (sim)
+ sim->proc_reset(id);
}
// Count number of contiguous 0 bits starting from the LSB.
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_M);
}
-
- yield_load_reservation();
}
void processor_t::disasm(insn_t insn)
void processor_t::set_csr(int which, reg_t val)
{
val = zext_xlen(val);
- reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
+ reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP
+ | ((ext != NULL) << IRQ_COP);
reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
switch (which)
{
state.minstret = (state.minstret >> 32 << 32) | (val & 0xffffffffU);
else
state.minstret = val;
+ // The ISA mandates that if an instruction writes instret, the write
+ // takes precedence over the increment to instret. However, Spike
+ // unconditionally increments instret after executing an instruction.
+ // Correct for this artifact by decrementing instret here.
+ state.minstret--;
break;
case CSR_MINSTRETH:
case CSR_MCYCLEH:
state.minstret = (val << 32) | (state.minstret << 32 >> 32);
+ state.minstret--; // See comment above.
break;
case CSR_SCOUNTEREN:
state.scounteren = val;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MTVAL: state.mtval = val; break;
case CSR_MISA: {
+ // the write is ignored if increasing IALIGN would misalign the PC
+ if (!(val & (1L << ('C' - 'A'))) && (state.pc & 2))
+ break;
+
if (!(val & (1L << ('F' - 'A'))))
val &= ~(1L << ('D' - 'A'));
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)
}
case CSR_SIP: return state.mip & state.mideleg;
case CSR_SIE: return state.mie & state.mideleg;
- case CSR_SEPC: return state.sepc;
+ case CSR_SEPC: return state.sepc & pc_alignment_mask();
case CSR_STVAL: return state.stval;
case CSR_STVEC: return state.stvec;
case CSR_SCAUSE:
case CSR_MSTATUS: return state.mstatus;
case CSR_MIP: return state.mip;
case CSR_MIE: return state.mie;
- case CSR_MEPC: return state.mepc;
+ case CSR_MEPC: return state.mepc & pc_alignment_mask();
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MTVAL: return state.mtval;
return v;
}
case CSR_DPC:
- return state.dpc;
+ return state.dpc & pc_alignment_mask();
case CSR_DSCRATCH:
return state.dscratch;
}