Support uarch counters (degenerately)

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 8ba87ed52bf38bae42451e998afeebfdd5da777a..4b282f6042ab9984bdc33d20673a1c522fdfb736 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -353,6 +353,23 @@ reg_t processor_t::get_pcr(int which)
     case CSR_FROMHOST:
       sim->get_htif()->tick(); // not necessary, but faster
       return state.fromhost;
+    case CSR_UARCH0:
+    case CSR_UARCH1:
+    case CSR_UARCH2:
+    case CSR_UARCH3:
+    case CSR_UARCH4:
+    case CSR_UARCH5:
+    case CSR_UARCH6:
+    case CSR_UARCH7:
+    case CSR_UARCH8:
+    case CSR_UARCH9:
+    case CSR_UARCH10:
+    case CSR_UARCH11:
+    case CSR_UARCH12:
+    case CSR_UARCH13:
+    case CSR_UARCH14:
+    case CSR_UARCH15:
+      return 0;
   }
   throw trap_illegal_instruction();
 }