const char* all_subsets = "IMAFDC";
max_xlen = 64;
+ cpuid = reg_t(2) << 62;
+
if (strncmp(p, "RV32", 4) == 0)
- max_xlen = 32, p += 4;
+ max_xlen = 32, cpuid = 0, p += 4;
else if (strncmp(p, "RV64", 4) == 0)
p += 4;
else if (strncmp(p, "RV", 2) == 0)
p += 2;
+ cpuid |= 1L << ('S' - 'A'); // advertise support for supervisor mode
+
if (!*p)
p = all_subsets;
else if (*p != 'I')
bad_isa_string(isa);
- memset(subsets, 0, sizeof(subsets));
-
while (*p) {
+ cpuid |= 1L << (*p - 'A');
+
if (auto next = strchr(all_subsets, *p)) {
- subsets[(int)*p] = true;
all_subsets = next + 1;
p++;
} else if (*p == 'X') {
mstatus = set_field(mstatus, MSTATUS_PRV, PRV_M);
mstatus = set_field(mstatus, MSTATUS_PRV1, PRV_S);
mstatus = set_field(mstatus, MSTATUS_PRV2, PRV_S);
- pc = 0x100;
+ pc = DEFAULT_MTVEC + 0x100;
load_reservation = -1;
}
void processor_t::set_histogram(bool value)
{
histogram_enabled = value;
+#ifndef RISCV_ENABLE_HISTOGRAM
+ if (value) {
+ fprintf(stderr, "PC Histogram support has not been properly enabled;");
+ fprintf(stderr, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
+ }
+#endif
}
void processor_t::reset(bool value)
{
int priv = get_field(state.mstatus, MSTATUS_PRV);
int ie = get_field(state.mstatus, MSTATUS_IE);
+ reg_t interrupts = state.mie & state.mip;
if (priv < PRV_M || (priv == PRV_M && ie)) {
- if (get_field(state.mstatus, MSTATUS_MSIP))
- raise_interrupt(IRQ_IPI);
+ if (interrupts & MIP_MSIP)
+ raise_interrupt(IRQ_SOFT);
+
+ if (interrupts & MIP_MTIP)
+ raise_interrupt(IRQ_TIMER);
if (state.fromhost != 0)
raise_interrupt(IRQ_HOST);
}
if (priv < PRV_S || (priv == PRV_S && ie)) {
- if (get_field(state.mstatus, MSTATUS_SSIP))
- raise_interrupt(IRQ_IPI);
+ if (interrupts & MIP_SSIP)
+ raise_interrupt(IRQ_SOFT);
- if (state.stip && get_field(state.mstatus, MSTATUS_STIE))
+ if (interrupts & MIP_STIP)
raise_interrupt(IRQ_TIMER);
}
}
return npc;
}
-static void update_timer(state_t* state, size_t instret)
-{
- uint64_t count0 = (uint64_t)(uint32_t)state->scount;
- state->scount += instret;
- uint64_t before = count0 - state->stimecmp;
- if (int64_t(before ^ (before + instret)) < 0)
- state->stip = true;
-}
-
-static size_t next_timer(state_t* state)
+void processor_t::check_timer()
{
- return state->stimecmp - (uint32_t)state->scount;
+ if (sim->rtc >= state.mtimecmp)
+ state.mip |= MIP_MTIP;
}
void processor_t::step(size_t n)
if (unlikely(!run || !n))
return;
- n = std::min(n, next_timer(&state) | 1U);
#define maybe_serialize() \
if (unlikely(pc == PC_SERIALIZE)) { \
pc = state.pc; \
state.serialized = true; \
- continue; \
+ break; \
}
try
{
+ check_timer();
take_interrupt();
if (unlikely(debug))
pc = execute_insn(this, pc, fetch); \
if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
if (unlikely(ic_entry->tag != pc)) break; \
+ if (unlikely(instret+1 == n)) break; \
instret++; \
state.pc = pc; \
}
}
catch(trap_t& t)
{
- state.pc = take_trap(t, pc);
+ take_trap(t, pc);
}
- update_timer(&state, instret);
+ state.minstret += instret;
+
+ // tail-recurse if we didn't execute as many instructions as we'd hoped
+ if (instret < n)
+ step(n - instret);
}
void processor_t::push_privilege_stack()
s = set_field(s, MSTATUS_PRV1, get_field(state.mstatus, MSTATUS_PRV));
s = set_field(s, MSTATUS_IE1, get_field(state.mstatus, MSTATUS_IE));
s = set_field(s, MSTATUS_PRV, PRV_M);
- s = set_field(s, MSTATUS_MPRV, PRV_M);
+ s = set_field(s, MSTATUS_MPRV, 0);
s = set_field(s, MSTATUS_IE, 0);
set_csr(CSR_MSTATUS, s);
}
set_csr(CSR_MSTATUS, s);
}
-reg_t processor_t::take_trap(trap_t& t, reg_t epc)
+void processor_t::take_trap(trap_t& t, reg_t epc)
{
if (debug)
fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
id, t.name(), epc);
- reg_t tvec = 0x40 * get_field(state.mstatus, MSTATUS_PRV);
+ state.pc = DEFAULT_MTVEC + 0x40 * get_field(state.mstatus, MSTATUS_PRV);
push_privilege_stack();
yield_load_reservation();
state.mcause = t.cause();
state.mepc = epc;
t.side_effects(&state); // might set badvaddr etc.
- return tvec;
}
void processor_t::deliver_ipi()
{
- state.mstatus |= MSTATUS_MSIP;
+ state.mip |= MIP_MSIP;
}
void processor_t::disasm(insn_t insn)
return priv == PRV_U || priv == PRV_S || priv == PRV_M;
}
-static bool validate_arch(int max_xlen, reg_t arch)
-{
- if (max_xlen == 64 && arch == UA_RV64)
- return true;
- return arch == UA_RV32;
-}
-
static bool validate_vm(int max_xlen, reg_t vm)
{
- if (max_xlen == 64 && vm == VM_SV39)
+ if (max_xlen == 64 && (vm == VM_SV39 || vm == VM_SV48))
return true;
if (max_xlen == 32 && vm == VM_SV32)
return true;
state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
break;
- case CSR_SCYCLE:
- case CSR_STIME:
- case CSR_SINSTRET:
- state.scount = val; break;
- case CSR_SCYCLEH:
- case CSR_STIMEH:
- case CSR_SINSTRETH:
- state.scount = (val << 32) | (uint32_t)state.scount;
+ case CSR_MTIME:
+ case CSR_STIMEW:
+ // this implementation ignores writes to MTIME
break;
- case CSR_MSTATUS:
- {
- if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_MPRV))
+ case CSR_MTIMEH:
+ case CSR_STIMEHW:
+ // this implementation ignores writes to MTIME
+ break;
+ case CSR_TIMEW:
+ val -= sim->rtc;
+ if (xlen == 32)
+ state.sutime_delta = (uint32_t)val | (state.sutime_delta >> 32 << 32);
+ else
+ state.sutime_delta = val;
+ break;
+ case CSR_TIMEHW:
+ val = ((val << 32) - sim->rtc) >> 32;
+ state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
+ break;
+ case CSR_CYCLEW:
+ case CSR_INSTRETW:
+ val -= state.minstret;
+ if (xlen == 32)
+ state.suinstret_delta = (uint32_t)val | (state.suinstret_delta >> 32 << 32);
+ else
+ state.suinstret_delta = val;
+ break;
+ case CSR_CYCLEHW:
+ case CSR_INSTRETHW:
+ val = ((val << 32) - state.minstret) >> 32;
+ state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
+ break;
+ case CSR_MSTATUS: {
+ if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_PRV | MSTATUS_PRV1 | MSTATUS_MPRV))
mmu->flush_tlb();
- reg_t mask = MSTATUS_SSIP | MSTATUS_MSIP | MSTATUS_IE | MSTATUS_IE1
- | MSTATUS_IE2 | MSTATUS_IE3 | MSTATUS_STIE | MSTATUS_FS;
- if (ext)
- mask |= MSTATUS_XS;
- state.mstatus = (state.mstatus & ~mask) | (val & mask);
+ reg_t mask = MSTATUS_IE | MSTATUS_IE1 | MSTATUS_IE2 | MSTATUS_MPRV
+ | MSTATUS_FS | (ext ? MSTATUS_XS : 0);
if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
- state.mstatus = (state.mstatus & ~MSTATUS_VM) | (val & MSTATUS_VM);
- if (validate_priv(get_field(val, MSTATUS_MPRV)))
- state.mstatus = (state.mstatus & ~MSTATUS_MPRV) | (val & MSTATUS_MPRV);
+ mask |= MSTATUS_VM;
if (validate_priv(get_field(val, MSTATUS_PRV)))
- state.mstatus = (state.mstatus & ~MSTATUS_PRV) | (val & MSTATUS_PRV);
+ mask |= MSTATUS_PRV;
if (validate_priv(get_field(val, MSTATUS_PRV1)))
- state.mstatus = (state.mstatus & ~MSTATUS_PRV1) | (val & MSTATUS_PRV1);
+ mask |= MSTATUS_PRV1;
if (validate_priv(get_field(val, MSTATUS_PRV2)))
- state.mstatus = (state.mstatus & ~MSTATUS_PRV2) | (val & MSTATUS_PRV2);
- if (validate_priv(get_field(val, MSTATUS_PRV3)))
- state.mstatus = (state.mstatus & ~MSTATUS_PRV3) | (val & MSTATUS_PRV3);
+ mask |= MSTATUS_PRV2;
+
+ state.mstatus = (state.mstatus & ~mask) | (val & mask);
bool dirty = (state.mstatus & MSTATUS_FS) == MSTATUS_FS;
dirty |= (state.mstatus & MSTATUS_XS) == MSTATUS_XS;
- xlen = 32;
- if (max_xlen == 32) {
+ if (max_xlen == 32)
state.mstatus = set_field(state.mstatus, MSTATUS32_SD, dirty);
- } else {
+ else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
- if (validate_arch(max_xlen, get_field(val, MSTATUS64_UA)))
- state.mstatus = (state.mstatus & ~MSTATUS64_UA) | (val & MSTATUS64_UA);
- if (validate_arch(max_xlen, get_field(val, MSTATUS64_SA)))
- state.mstatus = (state.mstatus & ~MSTATUS64_SA) | (val & MSTATUS64_SA);
- switch (get_field(state.mstatus, MSTATUS_PRV)) {
- case PRV_U: if (get_field(state.mstatus, MSTATUS64_UA)) xlen = 64; break;
- case PRV_S: if (get_field(state.mstatus, MSTATUS64_SA)) xlen = 64; break;
- case PRV_M: xlen = 64; break;
- default: abort();
- }
- }
+ // spike supports the notion of xlen < max_xlen, but current priv spec
+ // doesn't provide a mechanism to run RV32 software on an RV64 machine
+ xlen = max_xlen;
break;
}
- case CSR_SSTATUS:
- {
+ case CSR_MIP: {
+ reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP;
+ state.mip = (state.mip & ~mask) | (val & mask);
+ break;
+ }
+ case CSR_MIE: {
+ reg_t mask = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP;
+ state.mie = (state.mie & ~mask) | (val & mask);
+ break;
+ }
+ case CSR_SSTATUS: {
reg_t ms = state.mstatus;
- ms = set_field(ms, MSTATUS_SSIP, get_field(val, SSTATUS_SIP));
ms = set_field(ms, MSTATUS_IE, get_field(val, SSTATUS_IE));
ms = set_field(ms, MSTATUS_IE1, get_field(val, SSTATUS_PIE));
ms = set_field(ms, MSTATUS_PRV1, get_field(val, SSTATUS_PS));
- ms = set_field(ms, MSTATUS64_UA, get_field(val, SSTATUS_UA));
- ms = set_field(ms, MSTATUS_STIE, get_field(val, SSTATUS_TIE));
ms = set_field(ms, MSTATUS_FS, get_field(val, SSTATUS_FS));
ms = set_field(ms, MSTATUS_XS, get_field(val, SSTATUS_XS));
+ ms = set_field(ms, MSTATUS_MPRV, get_field(val, SSTATUS_MPRV));
return set_csr(CSR_MSTATUS, ms);
}
+ case CSR_SIP: {
+ reg_t mask = MIP_SSIP;
+ state.mip = (state.mip & ~mask) | (val & mask);
+ break;
+ }
+ case CSR_SIE: {
+ reg_t mask = MIP_SSIP | MIP_STIP;
+ state.mie = (state.mie & ~mask) | (val & mask);
+ break;
+ }
case CSR_SEPC: state.sepc = val; break;
case CSR_STVEC: state.stvec = val & ~3; break;
- case CSR_STIMECMP:
- state.stip = false;
- state.stimecmp = val;
- break;
- case CSR_SPTBR: state.sptbr = val & ~(PGSIZE-1); break;
+ case CSR_SPTBR: state.sptbr = zext_xlen(val & -PGSIZE); break;
case CSR_SSCRATCH: state.sscratch = val; break;
case CSR_MEPC: state.mepc = val; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
+ case CSR_MTIMECMP:
+ state.mip &= ~MIP_MTIP;
+ state.mtimecmp = val;
+ break;
case CSR_SEND_IPI: sim->send_ipi(val); break;
- case CSR_TOHOST:
+ case CSR_MTOHOST:
if (state.tohost == 0)
state.tohost = val;
break;
- case CSR_FROMHOST: state.fromhost = val; break;
+ case CSR_MFROMHOST: state.fromhost = val; break;
}
}
if (!supports_extension('F'))
break;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
- case CSR_CYCLE:
+ case CSR_MTIME:
+ case CSR_STIME:
+ case CSR_STIMEW:
+ return sim->rtc;
+ case CSR_MTIMEH:
+ case CSR_STIMEH:
+ case CSR_STIMEHW:
+ return sim->rtc >> 32;
case CSR_TIME:
+ case CSR_TIMEW:
+ return sim->rtc + state.sutime_delta;
+ case CSR_CYCLE:
+ case CSR_CYCLEW:
case CSR_INSTRET:
- case CSR_SCYCLE:
- case CSR_STIME:
- case CSR_SINSTRET:
- return state.scount;
- case CSR_CYCLEH:
+ case CSR_INSTRETW:
+ return state.minstret + state.suinstret_delta;
case CSR_TIMEH:
+ case CSR_TIMEHW:
+ if (xlen == 64)
+ break;
+ return (sim->rtc + state.sutime_delta) >> 32;
+ case CSR_CYCLEH:
case CSR_INSTRETH:
- case CSR_SCYCLEH:
- case CSR_STIMEH:
- case CSR_SINSTRETH:
+ case CSR_CYCLEHW:
+ case CSR_INSTRETHW:
if (xlen == 64)
break;
- return state.scount >> 32;
- case CSR_SSTATUS:
- {
+ return (state.minstret + state.suinstret_delta) >> 32;
+ case CSR_SSTATUS: {
reg_t ss = 0;
- ss = set_field(ss, SSTATUS_SIP, get_field(state.mstatus, MSTATUS_SSIP));
ss = set_field(ss, SSTATUS_IE, get_field(state.mstatus, MSTATUS_IE));
ss = set_field(ss, SSTATUS_PIE, get_field(state.mstatus, MSTATUS_IE1));
ss = set_field(ss, SSTATUS_PS, get_field(state.mstatus, MSTATUS_PRV1));
- ss = set_field(ss, SSTATUS_UA, get_field(state.mstatus, MSTATUS64_UA));
- ss = set_field(ss, SSTATUS_TIE, get_field(state.mstatus, MSTATUS_STIE));
- ss = set_field(ss, SSTATUS_TIP, state.stip);
ss = set_field(ss, SSTATUS_FS, get_field(state.mstatus, MSTATUS_FS));
ss = set_field(ss, SSTATUS_XS, get_field(state.mstatus, MSTATUS_XS));
+ ss = set_field(ss, SSTATUS_MPRV, get_field(state.mstatus, MSTATUS_MPRV));
if (get_field(state.mstatus, MSTATUS64_SD))
ss = set_field(ss, (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD), 1);
return ss;
}
+ case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
+ case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
case CSR_SEPC: return state.sepc;
case CSR_SBADADDR: return state.sbadaddr;
case CSR_STVEC: return state.stvec;
- case CSR_STIMECMP: return state.stimecmp;
case CSR_SCAUSE:
if (max_xlen > xlen)
return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1));
case CSR_SASID: return 0;
case CSR_SSCRATCH: return state.sscratch;
case CSR_MSTATUS: return state.mstatus;
+ case CSR_MIP: return state.mip;
+ case CSR_MIE: return state.mie;
case CSR_MEPC: return state.mepc;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MBADADDR: return state.mbadaddr;
- case CSR_TOHOST:
+ case CSR_MTIMECMP: return state.mtimecmp;
+ case CSR_MCPUID: return cpuid;
+ case CSR_MIMPID: return IMPL_ROCKET;
+ case CSR_MHARTID: return id;
+ case CSR_MTVEC: return DEFAULT_MTVEC;
+ case CSR_MTDELEG: return 0;
+ case CSR_MTOHOST:
sim->get_htif()->tick(); // not necessary, but faster
return state.tohost;
- case CSR_FROMHOST:
+ case CSR_MFROMHOST:
sim->get_htif()->tick(); // not necessary, but faster
return state.fromhost;
case CSR_SEND_IPI: return 0;
- case CSR_HARTID: return id;
case CSR_UARCH0:
case CSR_UARCH1:
case CSR_UARCH2:
projects / riscv-isa-sim.git / blobdiff