+// See LICENSE for license details.
+
#include "processor.h"
-#include <bfd.h>
-#include <dis-asm.h>
-#include <cmath>
-#include <cstdlib>
-#include <iostream>
+#include "extension.h"
#include "common.h"
#include "config.h"
#include "sim.h"
-#include "icsim.h"
-#include "softfloat.h"
-#include "platform.h" // softfloat isNaNF32UI, etc.
-#include "internals.h" // ditto
+#include "disasm.h"
+#include <cinttypes>
+#include <cmath>
+#include <cstdlib>
+#include <iostream>
+#include <assert.h>
+#include <limits.h>
+#include <stdexcept>
+
+processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
+ : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
+{
+ reset(true);
+ mmu->set_processor(this);
+
+ #define DECLARE_INSN(name, match, mask) REGISTER_INSN(this, name, match, mask)
+ #include "opcodes.h"
+ #undef DECLARE_INSN
+}
+
+processor_t::~processor_t()
+{
+}
-processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
- : sim(_sim), mmu(_mem,_memsz)
+void state_t::reset()
{
- memset(XPR,0,sizeof(XPR));
- memset(FPR,0,sizeof(FPR));
- pc = 0;
+ // the ISA guarantees on boot that the PC is 0x2000 and the the processor
+ // is in supervisor mode, and in 64-bit mode, if supported, with traps
+ // and virtual memory disabled.
+ sr = SR_S;
+#ifdef RISCV_ENABLE_64BIT
+ sr |= SR_S64;
+#endif
+ pc = 0x2000;
+
+ // the following state is undefined upon boot-up,
+ // but we zero it for determinism
+ XPR.reset();
+ FPR.reset();
+
evec = 0;
epc = 0;
badvaddr = 0;
cause = 0;
pcr_k0 = 0;
pcr_k1 = 0;
- tohost = 0;
- fromhost = 0;
count = 0;
compare = 0;
- set_sr(SR_S | SR_SX); // SX ignored if 64b mode not supported
- set_fsr(0);
+ cycle = 0;
+ fsr = 0;
- memset(counters,0,sizeof(counters));
+ load_reservation = -1;
+}
- // vector stuff
- vecbanks = 0xff;
- vecbanks_count = 8;
- utidx = -1;
- vlmax = 32;
- vl = 0;
- nxfpr_bank = 256;
- nxpr_use = 32;
- nfpr_use = 32;
- for (int i=0; i<MAX_UTS; i++)
- uts[i] = NULL;
+void processor_t::reset(bool value)
+{
+ if (run == !value)
+ return;
+ run = !value;
+
+ state.reset();
+}
- // a few assumptions about endianness, including freg_t union
- static_assert(BYTE_ORDER == LITTLE_ENDIAN);
- static_assert(sizeof(freg_t) == 8);
- static_assert(sizeof(reg_t) == 8);
+uint32_t processor_t::set_fsr(uint32_t val)
+{
+ uint32_t old_fsr = state.fsr;
+ state.fsr = val & ~FSR_ZERO; // clear FSR bits that read as zero
+ return old_fsr;
+}
- static_assert(sizeof(insn_t) == 4);
- static_assert(sizeof(uint128_t) == 16 && sizeof(int128_t) == 16);
+void processor_t::take_interrupt()
+{
+ uint32_t interrupts = (state.sr & SR_IP) >> SR_IP_SHIFT;
+ interrupts &= (state.sr & SR_IM) >> SR_IM_SHIFT;
- icsim = NULL;
- dcsim = NULL;
- itlbsim = NULL;
- dtlbsim = NULL;
+ if (interrupts && (state.sr & SR_EI))
+ for (int i = 0; ; i++, interrupts >>= 1)
+ if (interrupts & 1)
+ throw trap_t((1ULL << ((state.sr & SR_S64) ? 63 : 31)) + i);
}
-processor_t::~processor_t()
+void processor_t::step(size_t n, bool noisy)
{
- if(icsim)
- icsim->print_stats();
- delete icsim;
+ if(!run)
+ return;
- if(itlbsim)
- itlbsim->print_stats();
- delete itlbsim;
+ size_t i = 0;
+ reg_t npc = state.pc;
+ mmu_t* _mmu = mmu;
- if(dcsim)
- dcsim->print_stats();
- delete dcsim;
+ try
+ {
+ take_interrupt();
- if(dtlbsim)
- dtlbsim->print_stats();
- delete dtlbsim;
-}
+ // execute_insn fetches and executes one instruction
+ #define execute_insn(noisy) \
+ do { \
+ mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
+ if(noisy) disasm(fetch.insn.insn, npc); \
+ npc = fetch.func(this, fetch.insn.insn, npc); \
+ } while(0)
-void processor_t::init(uint32_t _id, icsim_t* default_icache,
- icsim_t* default_dcache)
-{
- id = _id;
+
+ // special execute_insn for commit log dumping
+#ifdef RISCV_ENABLE_COMMITLOG
+ //static disassembler disasmblr;
+ #undef execute_insn
+ #define execute_insn(noisy) \
+ do { \
+ mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
+ if(noisy) disasm(fetch.insn.insn, npc); \
+ bool in_spvr = state.sr & SR_S; \
+ if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
+ /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
+ npc = fetch.func(this, fetch.insn.insn, npc); \
+ } while(0)
+#endif
- for (int i=0; i<MAX_UTS; i++)
+ if(noisy) for( ; i < n; i++) // print out instructions as we go
+ execute_insn(true);
+ else
+ {
+ // unrolled for speed
+ for( ; n > 3 && i < n-3; i+=4)
+ {
+ execute_insn(false);
+ execute_insn(false);
+ execute_insn(false);
+ execute_insn(false);
+ }
+ for( ; i < n; i++)
+ execute_insn(false);
+ }
+
+ state.pc = npc;
+ }
+ catch(trap_t& t)
{
- uts[i] = new processor_t(sim, mmu.mem, mmu.memsz);
- uts[i]->id = id;
- uts[i]->set_sr(uts[i]->sr | SR_EF);
- uts[i]->set_sr(uts[i]->sr | SR_EV);
- uts[i]->utidx = i;
+ take_trap(npc, t, noisy);
}
- #ifdef RISCV_ENABLE_ICSIM
- icsim = new icsim_t(*default_icache);
- mmu.set_icsim(icsim);
- itlbsim = new icsim_t(1, 8, 4096, "ITLB");
- mmu.set_itlbsim(itlbsim);
- #endif
- #ifdef RISCV_ENABLE_ICSIM
- dcsim = new icsim_t(*default_dcache);
- mmu.set_dcsim(dcsim);
- dtlbsim = new icsim_t(1, 8, 4096, "DTLB");
- mmu.set_dtlbsim(dtlbsim);
- #endif
+ state.cycle += i;
+
+ // update timer and possibly register a timer interrupt
+ uint32_t old_count = state.count;
+ state.count += i;
+ if(old_count < state.compare && uint64_t(old_count) + i >= state.compare)
+ set_interrupt(IRQ_TIMER, true);
}
-void processor_t::set_sr(uint32_t val)
+void processor_t::take_trap(reg_t pc, trap_t& t, bool noisy)
{
- sr = val & ~SR_ZERO;
+ if (noisy)
+ fprintf(stderr, "core %3d: exception %s, epc 0x%016" PRIx64 "\n",
+ id, t.name(), pc);
+
+ // switch to supervisor, set previous supervisor bit, disable interrupts
+ set_pcr(PCR_SR, (((state.sr & ~SR_EI) | SR_S) & ~SR_PS & ~SR_PEI) |
+ ((state.sr & SR_S) ? SR_PS : 0) |
+ ((state.sr & SR_EI) ? SR_PEI : 0));
+
+ yield_load_reservation();
+ state.cause = t.cause();
+ state.epc = pc;
+ state.pc = state.evec;
+
+ t.side_effects(&state); // might set badvaddr etc.
+}
+
+void processor_t::deliver_ipi()
+{
+ if (run)
+ set_pcr(PCR_CLR_IPI, 1);
+}
+
+void processor_t::disasm(insn_t insn, reg_t pc)
+{
+ // the disassembler is stateless, so we share it
+ static disassembler disasm;
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
+ id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
+}
+
+reg_t processor_t::set_pcr(int which, reg_t val)
+{
+ reg_t old_pcr = get_pcr(which);
+
+ switch (which)
+ {
+ case PCR_SR:
+ state.sr = (val & ~SR_IP) | (state.sr & SR_IP);
#ifndef RISCV_ENABLE_64BIT
- sr &= ~(SR_SX | SR_UX);
+ state.sr &= ~(SR_S64 | SR_U64);
#endif
#ifndef RISCV_ENABLE_FPU
- sr &= ~SR_EF;
-#endif
-#ifndef RISCV_ENABLE_RVC
- sr &= ~SR_EC;
+ state.sr &= ~SR_EF;
#endif
#ifndef RISCV_ENABLE_VEC
- sr &= ~SR_EV;
+ state.sr &= ~SR_EV;
#endif
+ state.sr &= ~SR_ZERO;
+ mmu->flush_tlb();
+ break;
+ case PCR_EPC:
+ state.epc = val;
+ break;
+ case PCR_EVEC:
+ state.evec = val;
+ break;
+ case PCR_COUNT:
+ state.count = val;
+ break;
+ case PCR_COMPARE:
+ set_interrupt(IRQ_TIMER, false);
+ state.compare = val;
+ break;
+ case PCR_PTBR:
+ state.ptbr = val & ~(PGSIZE-1);
+ break;
+ case PCR_SEND_IPI:
+ sim->send_ipi(val);
+ break;
+ case PCR_CLR_IPI:
+ set_interrupt(IRQ_IPI, val & 1);
+ break;
+ case PCR_SUP0:
+ state.pcr_k0 = val;
+ break;
+ case PCR_SUP1:
+ state.pcr_k1 = val;
+ break;
+ case PCR_TOHOST:
+ if (state.tohost == 0)
+ state.tohost = val;
+ break;
+ case PCR_FROMHOST:
+ set_interrupt(IRQ_HOST, val != 0);
+ state.fromhost = val;
+ break;
+ }
- mmu.set_vm_enabled(sr & SR_VM);
- mmu.set_supervisor(sr & SR_S);
- mmu.flush_tlb();
-
- xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
+ return old_pcr;
}
-void processor_t::set_fsr(uint32_t val)
+reg_t processor_t::get_pcr(int which)
{
- fsr = val & ~FSR_ZERO;
+ switch (which)
+ {
+ case PCR_SR:
+ return state.sr;
+ case PCR_EPC:
+ return state.epc;
+ case PCR_BADVADDR:
+ return state.badvaddr;
+ case PCR_EVEC:
+ return state.evec;
+ case PCR_COUNT:
+ return state.count;
+ case PCR_COMPARE:
+ return state.compare;
+ case PCR_CAUSE:
+ return state.cause;
+ case PCR_PTBR:
+ return state.ptbr;
+ case PCR_ASID:
+ return 0;
+ case PCR_FATC:
+ mmu->flush_tlb();
+ return 0;
+ case PCR_HARTID:
+ return id;
+ case PCR_IMPL:
+ return 1;
+ case PCR_SUP0:
+ return state.pcr_k0;
+ case PCR_SUP1:
+ return state.pcr_k1;
+ case PCR_TOHOST:
+ return state.tohost;
+ case PCR_FROMHOST:
+ return state.fromhost;
+ }
+ return -1;
}
-void processor_t::vcfg()
+void processor_t::set_interrupt(int which, bool on)
{
- if (nxpr_use + nfpr_use < 2)
- vlmax = nxfpr_bank * vecbanks_count;
+ uint32_t mask = (1 << (which + SR_IP_SHIFT)) & SR_IP;
+ if (on)
+ state.sr |= mask;
else
- vlmax = (nxfpr_bank / (nxpr_use + nfpr_use - 1)) * vecbanks_count;
-
- vlmax = std::min(vlmax, MAX_UTS);
+ state.sr &= ~mask;
}
-void processor_t::setvl(int vlapp)
+reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
{
- vl = std::min(vlmax, vlapp);
+ throw trap_illegal_instruction();
}
-void processor_t::step(size_t n, bool noisy)
+insn_func_t processor_t::decode_insn(insn_t insn)
{
- size_t i = 0;
- while(1) try
- {
- for( ; i < n; i++)
- {
- uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
- interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
- if(interrupts && (sr & SR_ET))
- take_trap(trap_interrupt,noisy);
-
- insn_t insn = mmu.load_insn(pc, sr & SR_EC);
-
- reg_t npc = pc + insn_length(insn);
-
- if(noisy)
- disasm(insn,pc);
+ bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
- #include "execute.h"
-
- pc = npc;
- XPR[0] = 0;
+ auto key = insn.bits() & ((1L << opcode_bits)-1);
+ for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
+ if ((insn.bits() & it->second.mask) == it->second.match)
+ return rv64 ? it->second.rv64 : it->second.rv32;
- if(count++ == compare)
- cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
- }
- return;
- }
- catch(trap_t t)
- {
- i++;
- take_trap(t,noisy);
- }
- catch(vt_command_t cmd)
- {
- if (cmd == vt_command_stop)
- return;
- }
+ return &illegal_instruction;
}
-void processor_t::take_trap(trap_t t, bool noisy)
+void processor_t::register_insn(insn_desc_t desc)
{
- demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
- demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
- id, trap_name(t), (unsigned long long)pc);
- if(noisy)
- printf("core %3d: trap %s, pc 0x%016llx\n",
- id, trap_name(t), (unsigned long long)pc);
+ assert(desc.mask & 1);
+ if (opcode_bits == 0 || (desc.mask & ((1L << opcode_bits)-1)) != ((1L << opcode_bits)-1))
+ {
+ unsigned x = 0;
+ while ((desc.mask & ((1L << (x+1))-1)) == ((1L << (x+1))-1) &&
+ (opcode_bits == 0 || x <= opcode_bits))
+ x++;
+ opcode_bits = x;
+
+ decltype(opcode_map) new_map;
+ for (auto it = opcode_map.begin(); it != opcode_map.end(); ++it)
+ new_map.insert(std::make_pair(it->second.match & ((1L<<x)-1), it->second));
+ opcode_map = new_map;
+ }
- set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
- cause = (cause & ~CAUSE_EXCCODE) | (t << CAUSE_EXCCODE_SHIFT);
- epc = pc;
- pc = evec;
- badvaddr = mmu.get_badvaddr();
+ opcode_map.insert(std::make_pair(desc.match & ((1L<<opcode_bits)-1), desc));
}
-void processor_t::disasm(insn_t insn, reg_t pc)
+void processor_t::register_extension(extension_t* x)
{
- printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
-
- #ifdef RISCV_HAVE_LIBOPCODES
- disassemble_info info;
- INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
- info.flavour = bfd_target_unknown_flavour;
- info.arch = bfd_arch_mips;
- info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
- info.endian = BFD_ENDIAN_LITTLE;
- info.buffer = (bfd_byte*)&insn;
- info.buffer_length = sizeof(insn);
- info.buffer_vma = pc;
-
- int ret = print_insn_little_mips(pc, &info);
- demand(ret == (INSN_IS_RVC(insn.bits) ? 2 : 4), "disasm bug!");
- #else
- printf("unknown");
- #endif
- printf("\n");
+ for (auto insn : x->get_instructions())
+ register_insn(insn);
+ if (ext != NULL)
+ throw std::logic_error("only one extension may be registered");
+ ext = x;
+ x->set_processor(this);
}
projects / riscv-isa-sim.git / blobdiff