#include <iostream>
#include <assert.h>
#include <limits.h>
+#include <stdexcept>
processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
: sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
#define execute_insn(noisy) \
do { \
mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
- if(noisy) disasm(fetch.insn, npc); \
- npc = fetch.func(this, fetch.insn, npc); \
+ if(noisy) disasm(fetch.insn.insn, npc); \
+ npc = fetch.func(this, fetch.insn.insn, npc); \
} while(0)
+
+ // special execute_insn for commit log dumping
+#ifdef RISCV_ENABLE_COMMITLOG
+ //static disassembler disasmblr;
+ #undef execute_insn
+ #define execute_insn(noisy) \
+ do { \
+ mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
+ if(noisy) disasm(fetch.insn.insn, npc); \
+ bool in_spvr = state.sr & SR_S; \
+ if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
+ /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
+ npc = fetch.func(this, fetch.insn.insn, npc); \
+ } while(0)
+#endif
+
if(noisy) for( ; i < n; i++) // print out instructions as we go
execute_insn(true);
else
{
// the disassembler is stateless, so we share it
static disassembler disasm;
- fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
- id, state.pc, insn.bits, disasm.disassemble(insn).c_str());
+ fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
+ id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
}
reg_t processor_t::set_pcr(int which, reg_t val)
{
bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
- auto key = insn.bits & ((1L << opcode_bits)-1);
+ auto key = insn.bits() & ((1L << opcode_bits)-1);
for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
- if ((insn.bits & it->second.mask) == it->second.match)
+ if ((insn.bits() & it->second.mask) == it->second.match)
return rv64 ? it->second.rv64 : it->second.rv32;
return &illegal_instruction;