Added commit logging (--enable-commitlog). Also fixed disasm bug.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index a4a143037fbe02e5c45b99e8ffc532c0293295ca..5c0d784c3aa51ee72877dcc8875352c4f69249a9 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -12,6 +12,7 @@
 #include <iostream>
 #include <assert.h>
 #include <limits.h>
+#include <stdexcept>
 
 processor_t::processor_t(sim_t* _sim, mmu_t* _mmu, uint32_t _id)
   : sim(_sim), mmu(_mmu), ext(NULL), id(_id), opcode_bits(0)
@@ -102,10 +103,26 @@ void processor_t::step(size_t n, bool noisy)
     #define execute_insn(noisy) \
       do { \
         mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
-        if(noisy) disasm(fetch.insn, npc); \
-        npc = fetch.func(this, fetch.insn, npc); \
+        if(noisy) disasm(fetch.insn.insn, npc); \
+        npc = fetch.func(this, fetch.insn.insn, npc); \
       } while(0)
 
+    
+    // special execute_insn  for commit log dumping
+#ifdef RISCV_ENABLE_COMMITLOG
+    //static disassembler disasmblr; 
+    #undef execute_insn 
+    #define execute_insn(noisy) \
+      do { \
+        mmu_t::insn_fetch_t fetch = _mmu->load_insn(npc); \
+        if(noisy) disasm(fetch.insn.insn, npc); \
+        bool in_spvr = state.sr & SR_S; \
+        if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") ", npc, fetch.insn.insn.bits()); \
+        /*if (!in_spvr) fprintf(stderr, "\n0x%016" PRIx64 " (0x%08" PRIx32 ") %s  ", npc, fetch.insn.insn.bits(), disasmblr.disassemble(fetch.insn.insn).c_str());*/ \
+        npc = fetch.func(this, fetch.insn.insn, npc); \
+      } while(0)
+#endif
+
     if(noisy) for( ; i < n; i++) // print out instructions as we go
       execute_insn(true);
     else 
@@ -167,8 +184,8 @@ void processor_t::disasm(insn_t insn, reg_t pc)
 {
   // the disassembler is stateless, so we share it
   static disassembler disasm;
-  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIxFAST32 ") %s\n",
-          id, state.pc, insn.bits, disasm.disassemble(insn).c_str());
+  fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n",
+          id, state.pc, insn.bits(), disasm.disassemble(insn).c_str());
 }
 
 reg_t processor_t::set_pcr(int which, reg_t val)
@@ -213,10 +230,10 @@ reg_t processor_t::set_pcr(int which, reg_t val)
     case PCR_CLR_IPI:
       set_interrupt(IRQ_IPI, val & 1);
       break;
-    case PCR_K0:
+    case PCR_SUP0:
       state.pcr_k0 = val;
       break;
-    case PCR_K1:
+    case PCR_SUP1:
       state.pcr_k1 = val;
       break;
     case PCR_TOHOST:
@@ -261,9 +278,9 @@ reg_t processor_t::get_pcr(int which)
       return id;
     case PCR_IMPL:
       return 1;
-    case PCR_K0:
+    case PCR_SUP0:
       return state.pcr_k0;
-    case PCR_K1:
+    case PCR_SUP1:
       return state.pcr_k1;
     case PCR_TOHOST:
       return state.tohost;
@@ -291,9 +308,9 @@ insn_func_t processor_t::decode_insn(insn_t insn)
 {
   bool rv64 = (state.sr & SR_S) ? (state.sr & SR_S64) : (state.sr & SR_U64);
 
-  auto key = insn.bits & ((1L << opcode_bits)-1);
+  auto key = insn.bits() & ((1L << opcode_bits)-1);
   for (auto it = opcode_map.find(key); it != opcode_map.end() && it->first == key; ++it)
-    if ((insn.bits & it->second.mask) == it->second.match)
+    if ((insn.bits() & it->second.mask) == it->second.match)
       return rv64 ? it->second.rv64 : it->second.rv32;
 
   return &illegal_instruction;