Allow delegation of device interrupts

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ada5cd7b9877648bc84c5aa428687ecb30ee3a6c..63339b153935d902371cdf86fb33d2c45d6c2e95 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -254,7 +254,7 @@ static bool validate_vm(int max_xlen, reg_t vm)
 void processor_t::set_csr(int which, reg_t val)
 {
   val = zext_xlen(val);
-  reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_COP);
+  reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP);
   reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
   switch (which)
   {