[xcc,pk,sim,opcodes] added first RVC instruction

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 61f4ec181079ee7f6c6acdd88ed3337b25c86d9b..81ac42a7398360329ff44fb521ea2af5993313da 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -52,9 +52,12 @@ void processor_t::set_sr(uint32_t val)
 #ifndef RISCV_ENABLE_64BIT
   sr &= ~(SR_SX | SR_UX);
 #endif
-#ifndef RISCV_ENABLE_64BIT
+#ifndef RISCV_ENABLE_FPU
   sr &= ~SR_EF;
 #endif
+#ifdef RISCV_ENABLE_RVC
+  sr &= ~SR_C;
+#endif
 
   xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
 }
@@ -76,9 +79,9 @@ void processor_t::step(size_t n, bool noisy)
       if(interrupts && (sr & SR_ET))
         take_trap(trap_interrupt,noisy);
 
-      insn_t insn = mmu.load_insn(pc);
+      insn_t insn = mmu.load_insn(pc, rvc_mode);
   
-      reg_t npc = pc+sizeof(insn);
+      reg_t npc = pc + insn_length(insn);
 
       if(noisy)
         disasm(insn,pc);