Implement cycleh/instreth CSRs for RV32 (#172)

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 516a708f210f8b202b50060b662e2acab201c3f7..8cca49030e16ac878bcbd23e08ad3e0848a94f72 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -565,6 +565,11 @@ reg_t processor_t::get_csr(int which)
     case CSR_MINSTRET:
     case CSR_MCYCLE:
       return state.minstret;
+    case CSR_INSTRETH:
+    case CSR_CYCLEH:
+      if (ctr_ok && xlen == 32)
+        return state.minstret >> 32;
+      break;
     case CSR_MINSTRETH:
     case CSR_MCYCLEH:
       if (xlen == 32)