Turn off debugging.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 652d7c988c1c4cb75e5a1b03539c7d6474a50e5e..b120ddb1f55771aa16a9a8a75adca12d9c404247 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -198,7 +198,6 @@ void processor_t::set_privilege(reg_t prv)
 
 void processor_t::enter_debug_mode(uint8_t cause)
 {
-  fprintf(stderr, "enter_debug_mode(%d), mstatus=0x%lx, prv=0x%lx\n", cause, state.mstatus, state.prv);
   state.dcsr.cause = cause;
   state.dcsr.prv = state.prv;
   set_privilege(PRV_M);