debug: Checkpoint which somewhat works with OpenOCD v13, but still has some bugs.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index d6da193eba5baef80b0a56402507d8cc51243598..b2c2d344ec0e3db50120db13e09153d2e706d108 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -210,10 +210,8 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
   if (state.dcsr.cause) {
     if (t.cause() == CAUSE_BREAKPOINT) {
       state.pc = debug_rom_entry();
-      fprintf(stderr, "Breakpoint.");
     } else {
-      fprintf(stderr, "WE ARE IN DEBUG MODE, DEBUG_ROM_EXCEPTION\n");
-      state.pc = DEBUG_ROM_EXCEPTION;
+      state.pc = DEBUG_ROM_TVEC;
     }
     return;
   }