debug: Checkpoint which somewhat works with OpenOCD v13, but still has some bugs.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ef529fc20c1d6d885b2fc7b22abad7060302a68c..b2c2d344ec0e3db50120db13e09153d2e706d108 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -189,6 +189,7 @@ void processor_t::set_privilege(reg_t prv)
 
 void processor_t::enter_debug_mode(uint8_t cause)
 {
+  fprintf(stderr, "Entering debug mode because of cause %d", cause);
   state.dcsr.cause = cause;
   state.dcsr.prv = state.prv;
   set_privilege(PRV_M);
@@ -210,7 +211,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     if (t.cause() == CAUSE_BREAKPOINT) {
       state.pc = debug_rom_entry();
     } else {
-      state.pc = DEBUG_ROM_EXCEPTION;
+      state.pc = DEBUG_ROM_TVEC;
     }
     return;
   }