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Don't take interrupts while in Debug Mode.
[riscv-isa-sim.git]
/
riscv
/
processor.cc
diff --git
a/riscv/processor.cc
b/riscv/processor.cc
index 00eccc882d45713c999694f2c520c24cbe212846..b9fbe0ecb532a72bf7fa0385c0d599a7046f65e4 100644
(file)
--- a/
riscv/processor.cc
+++ b/
riscv/processor.cc
@@
-174,7
+174,7
@@
void processor_t::take_interrupt(reg_t pending_interrupts)
if (enabled_interrupts == 0)
enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
- if (enabled_interrupts)
+ if (
state.dcsr.cause == 0 &&
enabled_interrupts)
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
}