#include "common.h"
#include "config.h"
#include "sim.h"
+#include "mmu.h"
#include "htif.h"
#include "disasm.h"
#include <cinttypes>
{
parse_isa_string(isa);
- mmu = new mmu_t(sim->mem, sim->memsz);
- mmu->set_processor(this);
+ mmu = new mmu_t(sim, this);
reset(true);
const char* all_subsets = "imafdc";
max_xlen = 64;
- cpuid = reg_t(2) << 62;
+ isa = reg_t(2) << 62;
if (strncmp(p, "rv32", 4) == 0)
- max_xlen = 32, cpuid = 0, p += 4;
+ max_xlen = 32, isa = reg_t(1) << 30, p += 4;
else if (strncmp(p, "rv64", 4) == 0)
p += 4;
else if (strncmp(p, "rv", 2) == 0)
bad_isa_string(str);
}
- isa = "rv" + std::to_string(max_xlen) + p;
- cpuid |= 1L << ('s' - 'a'); // advertise support for supervisor mode
+ isa_string = "rv" + std::to_string(max_xlen) + p;
+ isa |= 1L << ('s' - 'a'); // advertise support for supervisor mode
while (*p) {
- cpuid |= 1L << (*p - 'a');
+ isa |= 1L << (*p - 'a');
if (auto next = strchr(all_subsets, *p)) {
all_subsets = next + 1;
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
+
+ // advertise support for supervisor and user modes
+ isa |= 1L << ('s' - 'a');
+ isa |= 1L << ('u' - 'a');
}
void state_t::reset()
{
memset(this, 0, sizeof(*this));
prv = PRV_M;
- pc = DEFAULT_MTVEC + 0x100;
+ pc = DEFAULT_RSTVEC;
load_reservation = -1;
}
void processor_t::take_interrupt()
{
- check_timer();
-
- reg_t interrupts = state.mip & state.mie;
+ reg_t pending_interrupts = state.mip & state.mie;
- reg_t m_interrupts = interrupts & ~state.mideleg;
reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
- if ((state.prv < PRV_M || (state.prv == PRV_M && mie)) && m_interrupts)
- raise_interrupt(ctz(m_interrupts));
+ reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
+ reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
- reg_t s_interrupts = interrupts & state.mideleg;
reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
- if ((state.prv < PRV_S || (state.prv == PRV_S && sie)) && s_interrupts)
- raise_interrupt(ctz(s_interrupts));
-}
+ reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
+ enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
-void processor_t::check_timer()
-{
- if (sim->rtc >= state.mtimecmp)
- state.mip |= MIP_MTIP;
+ if (enabled_interrupts)
+ raise_interrupt(ctz(enabled_interrupts));
}
static bool validate_priv(reg_t priv)
set_csr(CSR_MSTATUS, s);
set_privilege(PRV_S);
} else {
- state.pc = DEFAULT_MTVEC + 0x40 * state.prv;
+ state.pc = state.mtvec;
state.mcause = t.cause();
state.mepc = epc;
if (t.has_badaddr())
void processor_t::set_csr(int which, reg_t val)
{
val = zext_xlen(val);
- reg_t all_ints = MIP_SSIP | MIP_MSIP | MIP_STIP | MIP_MTIP | (1UL << IRQ_HOST);
- reg_t s_ints = MIP_SSIP | MIP_STIP;
+ reg_t delegable_ints = MIP_SSIP | MIP_STIP | (1 << IRQ_HOST) | (1 << IRQ_COP);
+ reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP;
switch (which)
{
case CSR_FFLAGS:
state.fflags = (val & FSR_AEXC) >> FSR_AEXC_SHIFT;
state.frm = (val & FSR_RD) >> FSR_RD_SHIFT;
break;
- case CSR_MTIME:
- case CSR_STIMEW:
- // this implementation ignores writes to MTIME
- break;
- case CSR_MTIMEH:
- case CSR_STIMEHW:
- // this implementation ignores writes to MTIME
- break;
- case CSR_TIMEW:
- val -= sim->rtc;
- if (xlen == 32)
- state.sutime_delta = val | (state.sutime_delta >> 32 << 32);
- else
- state.sutime_delta = val;
- break;
- case CSR_TIMEHW:
- val = ((val << 32) - sim->rtc) >> 32;
- state.sutime_delta = (val << 32) | (uint32_t)state.sutime_delta;
- break;
- case CSR_CYCLEW:
- case CSR_INSTRETW:
- val -= state.minstret;
- if (xlen == 32)
- state.suinstret_delta = val | (state.suinstret_delta >> 32 << 32);
- else
- state.suinstret_delta = val;
- break;
- case CSR_CYCLEHW:
- case CSR_INSTRETHW:
- val = ((val << 32) - state.minstret) >> 32;
- state.suinstret_delta = (val << 32) | (uint32_t)state.suinstret_delta;
- break;
case CSR_MSTATUS: {
- if ((val ^ state.mstatus) & (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV))
+ if ((val ^ state.mstatus) &
+ (MSTATUS_VM | MSTATUS_MPP | MSTATUS_MPRV | MSTATUS_PUM))
mmu->flush_tlb();
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
- | MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_FS
+ | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_PUM
| (ext ? MSTATUS_XS : 0);
if (validate_vm(max_xlen, get_field(val, MSTATUS_VM)))
break;
}
case CSR_MIP: {
- reg_t mask = all_ints &~ MIP_MTIP;
+ reg_t mask = MIP_SSIP | MIP_STIP | MIP_MSIP;
state.mip = (state.mip & ~mask) | (val & mask);
break;
}
state.mie = (state.mie & ~all_ints) | (val & all_ints);
break;
case CSR_MIDELEG:
- state.mideleg = (state.mideleg & ~s_ints) | (val & s_ints);
+ state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
reg_t mask = 0;
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
- case CSR_SSTATUS: {
- reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS;
- set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
- break;
- }
- case CSR_SIP: {
- reg_t mask = s_ints &~ MIP_STIP;
- state.mip = (state.mip & ~mask) | (val & mask);
+ case CSR_MUCOUNTEREN:
+ state.mucounteren = val & 7;
break;
- }
- case CSR_SIE: {
- reg_t mask = s_ints;
- state.mie = (state.mie & ~mask) | (val & mask);
+ case CSR_MSCOUNTEREN:
+ state.mscounteren = val & 7;
break;
+ case CSR_SSTATUS: {
+ reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+ | SSTATUS_XS | SSTATUS_PUM;
+ return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask));
}
+ case CSR_SIP:
+ return set_csr(CSR_MIP,
+ (state.mip & ~state.mideleg) | (val & state.mideleg));
+ case CSR_SIE:
+ return set_csr(CSR_MIE,
+ (state.mie & ~state.mideleg) | (val & state.mideleg));
case CSR_SEPC: state.sepc = val; break;
case CSR_STVEC: state.stvec = val >> 2 << 2; break;
- case CSR_SPTBR: state.sptbr = val & -PGSIZE; break;
+ case CSR_SPTBR: state.sptbr = val; break;
case CSR_SSCRATCH: state.sscratch = val; break;
case CSR_SCAUSE: state.scause = val; break;
case CSR_SBADADDR: state.sbadaddr = val; break;
case CSR_MEPC: state.mepc = val; break;
+ case CSR_MTVEC: state.mtvec = val >> 2 << 2; break;
case CSR_MSCRATCH: state.mscratch = val; break;
case CSR_MCAUSE: state.mcause = val; break;
case CSR_MBADADDR: state.mbadaddr = val; break;
- case CSR_MTIMECMP:
- state.mip &= ~MIP_MTIP;
- state.mtimecmp = val;
- break;
case CSR_MTOHOST:
if (state.tohost == 0)
state.tohost = val;
if (!supports_extension('F'))
break;
return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
- case CSR_MTIME:
- case CSR_STIME:
- case CSR_STIMEW:
- return sim->rtc;
- case CSR_MTIMEH:
- case CSR_STIMEH:
- case CSR_STIMEHW:
- return sim->rtc >> 32;
case CSR_TIME:
- case CSR_TIMEW:
- return sim->rtc + state.sutime_delta;
- case CSR_CYCLE:
- case CSR_CYCLEW:
case CSR_INSTRET:
- case CSR_INSTRETW:
- return state.minstret + state.suinstret_delta;
- case CSR_TIMEH:
- case CSR_TIMEHW:
- if (xlen == 64)
- break;
- return (sim->rtc + state.sutime_delta) >> 32;
- case CSR_CYCLEH:
- case CSR_INSTRETH:
- case CSR_CYCLEHW:
- case CSR_INSTRETHW:
- if (xlen == 64)
- break;
- return (state.minstret + state.suinstret_delta) >> 32;
+ case CSR_CYCLE:
+ if ((state.mucounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_CYCLE));
+ break;
+ case CSR_STIME:
+ case CSR_SINSTRET:
+ case CSR_SCYCLE:
+ if ((state.mscounteren >> (which & (xlen-1))) & 1)
+ return get_csr(which + (CSR_MCYCLE - CSR_SCYCLE));
+ break;
+ case CSR_MUCOUNTEREN: return state.mucounteren;
+ case CSR_MSCOUNTEREN: return state.mscounteren;
+ case CSR_MUCYCLE_DELTA: return 0;
+ case CSR_MUTIME_DELTA: return 0;
+ case CSR_MUINSTRET_DELTA: return 0;
+ case CSR_MSCYCLE_DELTA: return 0;
+ case CSR_MSTIME_DELTA: return 0;
+ case CSR_MSINSTRET_DELTA: return 0;
+ case CSR_MUCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MUINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSCYCLE_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSTIME_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MSINSTRET_DELTAH: if (xlen > 32) break; else return 0;
+ case CSR_MCYCLE: return state.minstret;
+ case CSR_MINSTRET: return state.minstret;
+ case CSR_MCYCLEH: if (xlen > 32) break; else return state.minstret >> 32;
+ case CSR_MINSTRETH: if (xlen > 32) break; else return state.minstret >> 32;
case CSR_SSTATUS: {
- reg_t sstatus = state.mstatus &
- (SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS);
+ reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
+ | SSTATUS_XS | SSTATUS_PUM;
+ reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)
sstatus |= (xlen == 32 ? SSTATUS32_SD : SSTATUS64_SD);
return sstatus;
}
- case CSR_SIP: return state.mip & (MIP_SSIP | MIP_STIP);
- case CSR_SIE: return state.mie & (MIP_SSIP | MIP_STIP);
+ case CSR_SIP: return state.mip & state.mideleg;
+ case CSR_SIE: return state.mie & state.mideleg;
case CSR_SEPC: return state.sepc;
case CSR_SBADADDR: return state.sbadaddr;
case CSR_STVEC: return state.stvec;
case CSR_MSCRATCH: return state.mscratch;
case CSR_MCAUSE: return state.mcause;
case CSR_MBADADDR: return state.mbadaddr;
- case CSR_MTIMECMP: return state.mtimecmp;
- case CSR_MCPUID: return cpuid;
- case CSR_MIMPID: return IMPL_ROCKET;
+ case CSR_MISA: return isa;
+ case CSR_MARCHID: return 0;
+ case CSR_MIMPID: return 0;
+ case CSR_MVENDORID: return 0;
case CSR_MHARTID: return id;
- case CSR_MTVEC: return DEFAULT_MTVEC;
+ case CSR_MTVEC: return state.mtvec;
case CSR_MEDELEG: return state.medeleg;
case CSR_MIDELEG: return state.mideleg;
case CSR_MTOHOST:
case CSR_MFROMHOST:
sim->get_htif()->tick(); // not necessary, but faster
return state.fromhost;
- case CSR_MIOBASE: return sim->memsz;
- case CSR_UARCH0:
- case CSR_UARCH1:
- case CSR_UARCH2:
- case CSR_UARCH3:
- case CSR_UARCH4:
- case CSR_UARCH5:
- case CSR_UARCH6:
- case CSR_UARCH7:
- case CSR_UARCH8:
- case CSR_UARCH9:
- case CSR_UARCH10:
- case CSR_UARCH11:
- case CSR_UARCH12:
- case CSR_UARCH13:
- case CSR_UARCH14:
- case CSR_UARCH15:
- return 0;
+ case CSR_MCFGADDR: return sim->config_string_addr;
}
throw trap_illegal_instruction();
}
projects / riscv-isa-sim.git / blobdiff