Trap on tdrdata registers when tdrselect[XLEN-1]=0

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ed9a83b8d551c2c1f4008d99a20aaa2377a2add5..dac5d5b37ff83ac858ef60297c4a7ebc8df54c2f 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -483,9 +483,6 @@ reg_t processor_t::get_csr(int which)
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case CSR_TDRSELECT: return 0;
-    case CSR_TDRDATA1: return 0;
-    case CSR_TDRDATA2: return 0;
-    case CSR_TDRDATA3: return 0;
     case CSR_DCSR:
       {
         uint32_t v = 0;