fixes to correctly simulate the vector unit

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 39a9ec096568cddf2c5ba3f0613848122a68b141..e12482015b3ce436e7781f9d152df975597e6914 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -299,6 +299,8 @@ reg_t processor_t::get_pcr(int which)
       return pcr_k1;
     case PCR_VECBANK:
       return vecbanks;
+    case PCR_VECCFG:
+      return nfpr_use << 18 | nxpr_use << 12 | vl;
     case PCR_TOHOST:
       return tohost;
     case PCR_FROMHOST: