Theoretically support trigger timing.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 57823f536a0f4c9d808635c20fa54ba627314fbd..e1f132e8b66ab11ba38c48f273bd1a50133bd77c 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -406,6 +406,10 @@ void processor_t::set_csr(int which, reg_t val)
         mc->store = get_field(val, MCONTROL_STORE);
         mc->load = get_field(val, MCONTROL_LOAD);
         // Assume we're here because of csrw.
+        if (mc->execute)
+          mc->timing = 0;
+        if (mc->load)
+          mc->timing = 1;
         trigger_updated();
       }
       break;