[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 35488104783be5d664c1361b6c327f1359cb05b5..e86536e4b4d05192bc5b678968c8103b272f856c 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -8,43 +8,10 @@
 #include "config.h"
 #include "sim.h"
 #include "icsim.h"
-#include "softfloat.h"
-#include "platform.h" // softfloat isNaNF32UI, etc.
-#include "internals.h" // ditto
 
-processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
-  : sim(_sim), mmu(_mem,_memsz)
+processor_t::processor_t(sim_t* _sim, mmu_t* _mmu)
+  : sim(_sim), mmu(*_mmu)
 {
-  memset(XPR,0,sizeof(XPR));
-  memset(FPR,0,sizeof(FPR));
-  pc = 0;
-  evec = 0;
-  epc = 0;
-  badvaddr = 0;
-  cause = 0;
-  pcr_k0 = 0;
-  pcr_k1 = 0;
-  tohost = 0;
-  fromhost = 0;
-  count = 0;
-  compare = 0;
-  set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
-  set_fsr(0);
-
-  memset(counters,0,sizeof(counters));
-
-  // vector stuff
-  vecbanks = 0xff;
-  vecbanks_count = 8;
-  utidx = -1;
-  vlmax = 8;
-  vl = 0;
-  nxfpr_bank = 256;
-  nxpr_use = 0;
-  nfpr_use = 0;
-  for (int i=0; i<MAX_UTS; i++)
-    uts[i] = NULL;
-
   // a few assumptions about endianness, including freg_t union
   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
   static_assert(sizeof(freg_t) == 8);
@@ -57,6 +24,8 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   dcsim = NULL;
   itlbsim = NULL;
   dtlbsim = NULL;
+
+  reset();
 }
 
 processor_t::~processor_t()
@@ -85,7 +54,7 @@ void processor_t::init(uint32_t _id, icsim_t* default_icache,
 
   for (int i=0; i<MAX_UTS; i++)
   {
-    uts[i] = new processor_t(sim, mmu.mem, mmu.memsz);
+    uts[i] = new processor_t(sim, &mmu);
     uts[i]->id = id;
     uts[i]->set_sr(uts[i]->sr | SR_EF);
     uts[i]->set_sr(uts[i]->sr | SR_EV);
@@ -106,6 +75,41 @@ void processor_t::init(uint32_t _id, icsim_t* default_icache,
   #endif
 }
 
+void processor_t::reset()
+{
+  run = false;
+
+  memset(XPR,0,sizeof(XPR));
+  memset(FPR,0,sizeof(FPR));
+
+  pc = 0;
+  evec = 0;
+  epc = 0;
+  badvaddr = 0;
+  cause = 0;
+  pcr_k0 = 0;
+  pcr_k1 = 0;
+  tohost = 0;
+  fromhost = 0;
+  count = 0;
+  compare = 0;
+  cycle = 0;
+  set_sr(SR_S | SR_SX);  // SX ignored if 64b mode not supported
+  set_fsr(0);
+
+  // vector stuff
+  vecbanks = 0xff;
+  vecbanks_count = 8;
+  utidx = -1;
+  vlmax = 32;
+  vl = 0;
+  nxfpr_bank = 256;
+  nxpr_use = 32;
+  nfpr_use = 32;
+  for (int i=0; i<MAX_UTS; i++)
+    uts[i] = NULL;
+}
+
 void processor_t::set_sr(uint32_t val)
 {
   sr = val & ~SR_ZERO;
@@ -149,34 +153,53 @@ void processor_t::setvl(int vlapp)
   vl = std::min(vlmax, vlapp);
 }
 
+void processor_t::take_interrupt()
+{
+  uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
+  interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
+
+  if(interrupts && (sr & SR_ET))
+    throw trap_interrupt;
+}
+
 void processor_t::step(size_t n, bool noisy)
 {
+  if(!run)
+    return;
+
   size_t i = 0;
   while(1) try
   {
-    for( ; i < n; i++)
-    {
-      uint32_t interrupts = (cause & CAUSE_IP) >> CAUSE_IP_SHIFT;
-      interrupts &= (sr & SR_IM) >> SR_IM_SHIFT;
-      if(interrupts && (sr & SR_ET))
-        take_trap(trap_interrupt,noisy);
+    take_interrupt();
 
-      insn_t insn = mmu.load_insn(pc, sr & SR_EC);
-  
-      reg_t npc = pc + insn_length(insn);
+    mmu_t& _mmu = mmu;
+    insn_t insn;
+    insn_func_t func;
+    reg_t npc = pc;
+    #define execute_insn(noisy) \
+      do { \
+        insn = _mmu.load_insn(npc, sr & SR_EC, &func); \
+        if(noisy) disasm(insn,pc); \
+        npc = func(this, insn, npc); \
+        pc = npc; \
+      } while(0)
 
-      if(noisy)
-        disasm(insn,pc);
-
-      #include "execute.h"
-  
-      pc = npc;
-      XPR[0] = 0;
-
-      if(count++ == compare)
-        cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
+    if(noisy) for( ; i < n; i++)
+      execute_insn(true);
+    else 
+    {
+      for( ; n > 3 && i < n-3; i+=4)
+      {
+        execute_insn(false);
+        execute_insn(false);
+        execute_insn(false);
+        execute_insn(false);
+      }
+      for( ; i < n; i++)
+        execute_insn(false);
     }
-    return;
+
+    break;
   }
   catch(trap_t t)
   {
@@ -185,9 +208,23 @@ void processor_t::step(size_t n, bool noisy)
   }
   catch(vt_command_t cmd)
   {
+    i++;
     if (cmd == vt_command_stop)
-      return;
+      break;
   }
+  catch(halt_t t)
+  {
+    reset();
+    return;
+  }
+
+  cycle += i;
+
+  typeof(count) old_count = count;
+  typeof(count) max_count = -1;
+  count += i;
+  if(old_count < compare && (count >= compare || old_count > max_count-i))
+    cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT);
 }
 
 void processor_t::take_trap(trap_t t, bool noisy)
@@ -206,6 +243,12 @@ void processor_t::take_trap(trap_t t, bool noisy)
   badvaddr = mmu.get_badvaddr();
 }
 
+void processor_t::deliver_ipi()
+{
+  cause |= 1 << (IPI_IRQ+CAUSE_IP_SHIFT);
+  run = true;
+}
+
 void processor_t::disasm(insn_t insn, reg_t pc)
 {
   printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
@@ -222,7 +265,7 @@ void processor_t::disasm(insn_t insn, reg_t pc)
   info.buffer_vma = pc;
 
   int ret = print_insn_little_mips(pc, &info);
-  demand(ret == (INSN_IS_RVC(insn.bits) ? 2 : 4), "disasm bug!");
+  demand(ret == insn_length(insn.bits), "disasm bug!");
   #else
   printf("unknown");
   #endif