[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index eea2ce2078a24409ebf5475a4511216154a7fb04..e86536e4b4d05192bc5b678968c8103b272f856c 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -9,8 +9,8 @@
 #include "sim.h"
 #include "icsim.h"
 
-processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
-  : sim(_sim), mmu(_mem,_memsz)
+processor_t::processor_t(sim_t* _sim, mmu_t* _mmu)
+  : sim(_sim), mmu(*_mmu)
 {
   // a few assumptions about endianness, including freg_t union
   static_assert(BYTE_ORDER == LITTLE_ENDIAN);
@@ -54,7 +54,7 @@ void processor_t::init(uint32_t _id, icsim_t* default_icache,
 
   for (int i=0; i<MAX_UTS; i++)
   {
-    uts[i] = new processor_t(sim, mmu.mem, mmu.memsz);
+    uts[i] = new processor_t(sim, &mmu);
     uts[i]->id = id;
     uts[i]->set_sr(uts[i]->sr | SR_EF);
     uts[i]->set_sr(uts[i]->sr | SR_EV);
@@ -172,13 +172,17 @@ void processor_t::step(size_t n, bool noisy)
   {
     take_interrupt();
 
-    #include "dispatch.h"
-
+    mmu_t& _mmu = mmu;
+    insn_t insn;
+    insn_func_t func;
+    reg_t npc = pc;
     #define execute_insn(noisy) \
-      do { insn_t insn = mmu.load_insn(pc, sr & SR_EC); \
-      if(noisy) disasm(insn,pc); \
-      pc = dispatch_table[dispatch_index(insn)](this, insn, pc); \
-      XPR[0] = 0; } while(0)
+      do { \
+        insn = _mmu.load_insn(npc, sr & SR_EC, &func); \
+        if(noisy) disasm(insn,pc); \
+        npc = func(this, insn, npc); \
+        pc = npc; \
+      } while(0)
 
     if(noisy) for( ; i < n; i++)
       execute_insn(true);