Initialize mtvec to DEFAULT_MTVEC

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index ccbbd1632102a42b42c594a7e692fcc407642ffb..f4c64ac564033727ebf960595d5e0f56fb06b528 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -115,6 +115,7 @@ void state_t::reset()
   memset(this, 0, sizeof(*this));
   prv = PRV_M;
   pc = DEFAULT_RSTVEC;
+  mtvec = DEFAULT_MTVEC;
   load_reservation = -1;
 }