[sim] add disable option for vector

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 318590870a647eaf71a7ccf9ee4483b630748b74..f9c8bea1900c846e7964a05e65f8964570975909 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -77,6 +77,9 @@ void processor_t::set_sr(uint32_t val)
 #ifndef RISCV_ENABLE_RVC
   sr &= ~SR_EC;
 #endif
+#ifndef RISCV_ENABLE_VEC
+  sr &= ~SR_EV;
+#endif
 
   xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
 }