Rip out RVC for now

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index c2d0ea5709a2939833abde117f69e50c16ddcd11..08c367298738151e95822b0c15aecf1e194d5e43 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -109,18 +109,4 @@ private:
   reg_t illegal_instruction(insn_t insn, reg_t pc);
 };
 
-#ifndef RISCV_ENABLE_RVC
-# define set_pc(x) \
-  do { if ((x) & 3) \
-         throw trap_instruction_address_misaligned; \
-       npc = (x); \
-     } while(0)
-#else
-# define set_pc(x) \
-  do { if ((x) & ((sr & SR_EC) ? 1 : 3)) \
-         throw trap_instruction_address_misaligned; \
-       npc = (x); \
-     } while(0)
-#endif
-
 #endif