Disassemble RVC instructions based on XLEN

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 730ae787c60c99a2805c314fc9e64ea2ddf8bb10..090ebe7a155a9157f2cc6c8e0d112d05f120acfc 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -106,9 +106,8 @@ public:
 
   void set_debug(bool value);
   void set_histogram(bool value);
-  void reset(bool value);
+  void reset();
   void step(size_t n); // run for n cycles
-  bool running() { return run; }
   void set_csr(int which, reg_t val);
   void raise_interrupt(reg_t which);
   reg_t get_csr(int which);
@@ -122,6 +121,7 @@ public:
   void set_privilege(reg_t);
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
   void update_histogram(reg_t pc);
+  const disassembler_t* get_disassembler() { return disassembler; }
 
   void register_insn(insn_desc_t);
   void register_extension(extension_t*);
@@ -144,7 +144,6 @@ private:
   unsigned xlen;
   reg_t isa;
   std::string isa_string;
-  bool run; // !reset
   bool histogram_enabled;
   bool halt_on_reset;
 
@@ -158,6 +157,7 @@ private:
   void take_interrupt(); // take a trap if any interrupts are pending
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
+  int paddr_bits();
 
   void enter_debug_mode(uint8_t cause);