Disassemble RVC instructions based on XLEN

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 8ac8507c8705998480fcbe1dadedffbbb1117da7..090ebe7a155a9157f2cc6c8e0d112d05f120acfc 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -35,7 +35,6 @@ typedef struct
 {
   uint8_t prv;
   bool step;
-  bool debugint;
   bool ebreakm;
   bool ebreakh;
   bool ebreaks;
@@ -82,6 +81,14 @@ struct state_t
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
 
+  // When true, execute a single instruction and then enter debug mode.  This
+  // can only be set by executing dret.
+  enum {
+      STEP_NONE,
+      STEP_STEPPING,
+      STEP_STEPPED
+  } single_step;
+
   reg_t load_reservation;
 
 #ifdef RISCV_ENABLE_COMMITLOG
@@ -90,27 +97,17 @@ struct state_t
 #endif
 };
 
-typedef enum {
-      HR_NONE,
-      HR_STEPPED,       // A single step was completed
-      HR_SWBP,          // sbreak was executed
-      HR_INTERRUPT,     // Execution interrupted by debugger
-      HR_CMDLINE,       // Command line requested that the processor start halted
-      HR_ATTACHED       // Halted because a debugger attached
-} halt_reason_t;
-
 // this class represents one processor in a RISC-V machine.
 class processor_t : public abstract_device_t
 {
 public:
-  processor_t(const char* isa, sim_t* sim, uint32_t id);
+  processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset=false);
   ~processor_t();
 
   void set_debug(bool value);
   void set_histogram(bool value);
-  void reset(bool value);
+  void reset();
   void step(size_t n); // run for n cycles
-  bool running() { return run; }
   void set_csr(int which, reg_t val);
   void raise_interrupt(reg_t which);
   reg_t get_csr(int which);
@@ -124,6 +121,7 @@ public:
   void set_privilege(reg_t);
   void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
   void update_histogram(reg_t pc);
+  const disassembler_t* get_disassembler() { return disassembler; }
 
   void register_insn(insn_desc_t);
   void register_extension(extension_t*);
@@ -132,6 +130,9 @@ public:
   bool load(reg_t addr, size_t len, uint8_t* bytes);
   bool store(reg_t addr, size_t len, const uint8_t* bytes);
 
+  // When true, display disassembly of each instruction that's executed.
+  bool debug;
+
 private:
   sim_t* sim;
   mmu_t* mmu; // main memory is always accessed via the mmu
@@ -143,10 +144,8 @@ private:
   unsigned xlen;
   reg_t isa;
   std::string isa_string;
-  bool run; // !reset
-  // When true, display disassembly of each instruction that's executed.
-  bool debug;
   bool histogram_enabled;
+  bool halt_on_reset;
 
   std::vector<insn_desc_t> instructions;
   std::map<reg_t,uint64_t> pc_histogram;
@@ -158,6 +157,7 @@ private:
   void take_interrupt(); // take a trap if any interrupts are pending
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
+  int paddr_bits();
 
   void enter_debug_mode(uint8_t cause);
 
@@ -165,7 +165,6 @@ private:
   friend class mmu_t;
   friend class rtc_t;
   friend class extension_t;
-  friend class gdbserver_t;
 
   void parse_isa_string(const char* isa);
   void build_opcode_map();