uint32_t frm;
bool serialized; // whether timer CSRs are in a well-defined state
+ // When true, execute a single instruction and then enter debug mode. This
+ // can only be set by executing dret.
+ enum {
+ STEP_NONE,
+ STEP_STEPPING,
+ STEP_STEPPED
+ } single_step;
+
reg_t load_reservation;
#ifdef RISCV_ENABLE_COMMITLOG
class processor_t : public abstract_device_t
{
public:
- processor_t(const char* isa, sim_t* sim, uint32_t id);
+ processor_t(const char* isa, sim_t* sim, uint32_t id, bool halt_on_reset=false);
~processor_t();
void set_debug(bool value);
void set_histogram(bool value);
- void reset(bool value);
+ void reset();
void step(size_t n); // run for n cycles
- bool running() { return run; }
void set_csr(int which, reg_t val);
void raise_interrupt(reg_t which);
reg_t get_csr(int which);
void set_privilege(reg_t);
void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
void update_histogram(reg_t pc);
+ const disassembler_t* get_disassembler() { return disassembler; }
void register_insn(insn_desc_t);
void register_extension(extension_t*);
unsigned xlen;
reg_t isa;
std::string isa_string;
- bool run; // !reset
bool histogram_enabled;
+ bool halt_on_reset;
std::vector<insn_desc_t> instructions;
std::map<reg_t,uint64_t> pc_histogram;
void take_interrupt(); // take a trap if any interrupts are pending
void take_trap(trap_t& t, reg_t epc); // take an exception
void disasm(insn_t insn); // disassemble and print an instruction
+ int paddr_bits();
void enter_debug_mode(uint8_t cause);