abstract regfile behind object

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 1e007a8fbdbb1829bdfbb673feaa4687578dbbb4..09fac00277b6796023b359e868ddd5192c21b57c 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -28,8 +28,8 @@ private:
   mmu_t& mmu; // main memory is always accessed via the mmu
 
   // user-visible architected state
-  reg_t XPR[NXPR];
-  freg_t FPR[NFPR];
+  regfile_t<reg_t, NXPR, true> XPR;
+  regfile_t<freg_t, NFPR, false> FPR;
   reg_t pc;
 
   // counters