Fix debug reset.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 071f4581f0e8091c6a92016cd8b6f824328843fa..2d82d917dd8d5b7e4dee2c6848c8e75e5b002211 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -194,12 +194,6 @@ public:
   bool slow_path();
   bool halted() { return state.dcsr.cause ? true : false; }
   bool halt_request;
-  // The unique debug rom address that this hart jumps to when entering debug
-  // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive.
-  uint32_t debug_rom_entry() {
-    fprintf(stderr, "Debug_rom_entry called for id %d = %x\n", id, DEBUG_ROM_ENTRY + 4*id);
-    return DEBUG_ROM_ENTRY + 4 * id;
-  }
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
@@ -322,6 +316,9 @@ private:
   void build_opcode_map();
   void register_base_instructions();
   insn_func_t decode_insn(insn_t insn);
+
+  // Track repeated executions for processor_t::disasm()
+  uint64_t last_pc, last_bits, executions;
 };
 
 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);