Fix debug reset.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 7e9e932f7b13a8c5cd4cb3275c3a697913c6f0f1..2d82d917dd8d5b7e4dee2c6848c8e75e5b002211 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -8,6 +8,7 @@
 #include <string>
 #include <vector>
 #include <map>
+#include "debug_rom/debug_rom_defines.h"
 
 class processor_t;
 class mmu_t;
@@ -191,6 +192,8 @@ public:
   bool debug;
   // When true, take the slow simulation path.
   bool slow_path();
+  bool halted() { return state.dcsr.cause ? true : false; }
+  bool halt_request;
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
@@ -313,6 +316,9 @@ private:
   void build_opcode_map();
   void register_base_instructions();
   insn_func_t decode_insn(insn_t insn);
+
+  // Track repeated executions for processor_t::disasm()
+  uint64_t last_pc, last_bits, executions;
 };
 
 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);