Implement hartstatus field.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 8a9ff47fdfdc6f02312f3328ae5710fc5dbcd7e3..32dc9cd2443a709ba0bb3e60db3afaa07d2d5456 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -192,6 +192,7 @@ public:
   bool debug;
   // When true, take the slow simulation path.
   bool slow_path();
+  bool halted() { return state.dcsr.cause ? true : false; }
 
   // Return the index of a trigger that matched, or -1.
   inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)