Only print commit log if instruction commits

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e2847faefaf1ff60ff890d95ad0521502f8f00a3..41268f9d2b40575e8f64954154e153700a9561b9 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -23,6 +23,12 @@ struct insn_desc_t
   insn_func_t rv64;
 };
 
+struct commit_log_reg_t
+{
+  uint32_t addr;
+  reg_t data;
+};
+
 // architectural state of a RISC-V hart
 struct state_t
 {
@@ -49,6 +55,10 @@ struct state_t
   uint32_t frm;
 
   reg_t load_reservation;
+
+#ifdef RISCV_ENABLE_COMMITLOG
+  commit_log_reg_t log_reg_write;
+#endif
 };
 
 // this class represents one processor in a RISC-V machine.