Merge branch 'master' into trigger

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index d5e8bc05a3841392423d5b81c7c60728766250e9..4d8dd640b72a921b9de01d03b4528a096f749305 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -105,8 +105,8 @@ struct state_t
   reg_t mip;
   reg_t medeleg;
   reg_t mideleg;
-  reg_t mucounteren;
-  reg_t mscounteren;
+  uint32_t mucounteren;
+  uint32_t mscounteren;
   reg_t sepc;
   reg_t sbadaddr;
   reg_t sscratch;