Gutting direct-access gdb.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index e0142995c1c09d8eb5ae6ce829738d4e8ec1dbeb..8ac8507c8705998480fcbe1dadedffbbb1117da7 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -107,8 +107,6 @@ public:
   ~processor_t();
 
   void set_debug(bool value);
-  void set_halted(bool value, halt_reason_t reason);
-  void set_single_step(bool value);
   void set_histogram(bool value);
   void reset(bool value);
   void step(size_t n); // run for n cycles
@@ -148,12 +146,6 @@ private:
   bool run; // !reset
   // When true, display disassembly of each instruction that's executed.
   bool debug;
-  // TODO: Should this just be rolled into `run`?
-  bool halted;  // When true, no instructions are executed.
-  halt_reason_t halt_reason;        // Why is halted true?
-  // When true, execute exactly one instruction (even if halted is true), then
-  // set halted to true and single_step to false.
-  bool single_step;
   bool histogram_enabled;
 
   std::vector<insn_desc_t> instructions;
@@ -167,6 +159,8 @@ private:
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
 
+  void enter_debug_mode(uint8_t cause);
+
   friend class sim_t;
   friend class mmu_t;
   friend class rtc_t;