[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 10abe1495a5decfc38e2b54c727c298a5665dad1..8b2d2bcee87d468b9e98bc7c3a4ed68512b25857 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -4,17 +4,19 @@
 #include "decode.h"
 #include <cstring>
 #include "trap.h"
-#include "mmu.h"
 #include "icsim.h"
 
 #define MAX_UTS 2048
 
+class processor_t;
+class mmu_t;
+typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
 class sim_t;
 
 class processor_t
 {
 public:
-  processor_t(sim_t* _sim, char* _mem, size_t _memsz);
+  processor_t(sim_t* _sim, mmu_t* _mmu);
   ~processor_t();
   void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache);
   void step(size_t n, bool noisy);
@@ -51,7 +53,7 @@ private:
   int xprlen;
 
   // shared memory
-  mmu_t mmu;
+  mmu_t& mmu;
 
   // counters
   reg_t cycle;
@@ -87,8 +89,9 @@ private:
   icsim_t* dtlbsim;
 
   friend class sim_t;
-  
-  #include "dispatch_decl.h"
+  friend class mmu_t;
+
+  #include "dispatch.h"
 };
 
 #endif