[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 5c524c0fef183834c5b523f3c91ffc7d2f704a0f..8b2d2bcee87d468b9e98bc7c3a4ed68512b25857 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -4,20 +4,23 @@
 #include "decode.h"
 #include <cstring>
 #include "trap.h"
-#include "mmu.h"
 #include "icsim.h"
 
-#define MAX_UTS 32
+#define MAX_UTS 2048
 
+class processor_t;
+class mmu_t;
+typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
 class sim_t;
 
 class processor_t
 {
 public:
-  processor_t(sim_t* _sim, char* _mem, size_t _memsz);
+  processor_t(sim_t* _sim, mmu_t* _mmu);
   ~processor_t();
-  void init(uint32_t _id);
+  void init(uint32_t _id, icsim_t* defualt_icache, icsim_t* default_dcache);
   void step(size_t n, bool noisy);
+  void deliver_ipi();
 
 private:
   sim_t* sim;
@@ -41,6 +44,8 @@ private:
   uint32_t count;
   uint32_t compare;
 
+  bool run;
+
   // unprivileged control registers
   uint32_t fsr;
 
@@ -48,12 +53,14 @@ private:
   int xprlen;
 
   // shared memory
-  mmu_t mmu;
+  mmu_t& mmu;
 
   // counters
-  reg_t counters[32];
+  reg_t cycle;
 
   // functions
+  void reset();
+  void take_interrupt();
   void set_sr(uint32_t val);
   void set_fsr(uint32_t val);
   void take_trap(trap_t t, bool noisy);
@@ -63,20 +70,28 @@ private:
   void vcfg();
   void setvl(int vlapp);
 
+  reg_t vecbanks;
+  uint32_t vecbanks_count;
+
   bool utmode;
   int utidx;
   int vlmax;
   int vl;
-  int nxpr_all;
-  int nfpr_all;
+  int nxfpr_bank;
   int nxpr_use;
   int nfpr_use;
   processor_t* uts[MAX_UTS];
 
-  // icache sim
+  // cache sim
   icsim_t* icsim;
+  icsim_t* dcsim;
+  icsim_t* itlbsim;
+  icsim_t* dtlbsim;
 
   friend class sim_t;
+  friend class mmu_t;
+
+  #include "dispatch.h"
 };
 
 #endif